* Add memory checks for prover_input and range_checks for prover_input, syscalls and exceptions
* Replace u32 by U256, and remove extra CTLs
* Add column in ArithmeticStark to use ctl_arithmetic_base_rows for is_range_check
* Fix CTLs and circuit constraint.
* Fix CTLs
* Remove extra shift CTL.
* Change order of inputs for the arithmetic shift operations. Add SHR test. Fix max number of bit shifts. Cleanup.
* Fix SHR in the case shift >= 256
* Limit visibility of helper functions
* Change padding rule for CPU
* Disable memory channels for padding rows
* Apply some of Jacqueline's comments
* Update halt routine
* Add clarifying comment
* Redundant constraints and padding bug
* Revert "Remove is_bootstrap_kernel column"
This reverts commit 49d92cb8f1b0ae9de76872f76af4429699ff692f.
* Make halt_state implicit
* Move halting logic constraints to dedicated module
* Include new module
* Update some comments
* Combine mstore_general and mload_general into one flag
* Add comments and make stack constraints cleaner.
* Fix number of native instructions
* Ordering
* Cleanup
* Update calls to stack eval from latest main
---------
Co-authored-by: Robin Salen <salenrobin@gmail.com>
* Combine FP254 flags
* Combine basic binary ops together and do CTL with opcode value
* Combine ternary ops together
* Combine MUL DIV and MOD
* Combine shift operations
* Combine byte with other binary ops
* Fix tests
* Clean leftover comment
* Update from latest main
* Put the 'is_simulated' flag inside the Operation enum
* Cleaner way to handle "simulated" operations SHL and SHR.
* Fix comments.
* Minor: suggestion for re-expressing `combined_ops`.
* Update comment
---------
Co-authored-by: Hamish Ivey-Law <hamish@ivey-law.name>
* Add corresponding arithmetic operations to shift ones
* Include SHL/SHR in the arithmetic CTL
* Prevent overflow
* Expand documentation for ctl_data_ternops()
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
Lots of little bugs!
- The Keccak sponge table's padding logic was wrong, it was mixing up the number of rows with the number of hashes.
- The Keccak sponge table's Keccak-looking data was wrong - input to Keccak-f should be after xor'ing in the block.
- The Keccak sponge table's logic-looking filter was wrong. We do 5 logic CTLs for any final-block row, even if some of the xors are with 0s from Keccak padding.
- The CPU was using the wrong/outdated output memory channel for its Keccak sponge and logic CTLs.
- The Keccak table just didn't have a way to filter out padding rows. I added a filter column for this.
- The Keccak table wasn't remembering the original preimage of a permutation; lookers were seeing the preimage of the final step. I added columns for the original preimage.
- `ctl_data_logic` was using the wrong memory channel
- Kernel bootloading generation was using the wrong length for its Keccak sponge CTL, and its `keccak_sponge_log` was seeing the wrong clock since it was called after adding the final bootloading row.
