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Fix logic CTL

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This commit is contained in:
Robin Salen 2023-08-11 09:23:58 -04:00
parent ee9ce4c59d
commit 437f57a862
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GPG Key ID: FB87BACFB3CB2007
3 changed files with 9 additions and 7 deletions
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4
evm/src/cpu/cpu_stark.rs
View File

@ -83,7 +83,9 @@ fn ctl_data_ternops<F: Field>(ops: &[usize], is_shift: bool) -> Vec<Column<F>> {
}
pub fn ctl_data_logic<F: Field>() -> Vec<Column<F>> {
ctl_data_binops(&[COL_MAP.op.and_or, COL_MAP.op.xor])
let mut res = vec![Column::le_bits(COL_MAP.opcode_bits)];
res.extend(ctl_data_binops(&[]));
res
}
pub fn ctl_filter_logic<F: Field>() -> Column<F> {

3
evm/src/keccak_sponge/keccak_sponge_stark.rs
View File

@ -103,8 +103,7 @@ pub(crate) fn ctl_looking_logic<F: Field>(i: usize) -> Vec<Column<F>> {
let cols = KECCAK_SPONGE_COL_MAP;
let mut res = vec![
Column::zero(), // is_and_or
Column::one(), // is_xor
Column::constant(F::from_canonical_u8(0x18)), // is_xor
];
// Input 0 contains some of the sponge's original rate chunks. If this is the last CTL, we won't

9
evm/src/logic.rs
View File

@ -52,10 +52,11 @@ pub(crate) mod columns {
}
pub fn ctl_data<F: Field>() -> Vec<Column<F>> {
let mut res = vec![
Column::sum([columns::IS_AND, columns::IS_OR]),
Column::single(columns::IS_XOR),
];
let mut res = vec![Column::linear_combination([
(columns::IS_AND, F::from_canonical_u8(0x16)),
(columns::IS_OR, F::from_canonical_u8(0x17)),
(columns::IS_XOR, F::from_canonical_u8(0x18)),
])];
res.extend(columns::limb_bit_cols_for_input(columns::INPUT0).map(Column::le_bits));
res.extend(columns::limb_bit_cols_for_input(columns::INPUT1).map(Column::le_bits));
res.extend(columns::RESULT.map(Column::single));