* Remove extra shift CTL.
* Change order of inputs for the arithmetic shift operations. Add SHR test. Fix max number of bit shifts. Cleanup.
* Fix SHR in the case shift >= 256
* Limit visibility of helper functions
* Combine FP254 flags
* Combine basic binary ops together and do CTL with opcode value
* Combine ternary ops together
* Combine MUL DIV and MOD
* Combine shift operations
* Combine byte with other binary ops
* Fix tests
* Clean leftover comment
* Update from latest main
* Put the 'is_simulated' flag inside the Operation enum
* Cleaner way to handle "simulated" operations SHL and SHR.
* Fix comments.
* Minor: suggestion for re-expressing `combined_ops`.
* Update comment
---------
Co-authored-by: Hamish Ivey-Law <hamish@ivey-law.name>
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
* Unify handling of ADD, SUB, LT, GT under the formula x+y=z+cy*2^256.
* Rename general column ranges to "registers" instead of "inputs".
* Rename 'compare' module to 'addcc'.
* Update comments.
* Enforce length equality in iteration.
* Address William's PR comments.
* Simplify loop and remove clippy.
* Offset auxiliary coefficients so they're always positive.
* Split mul aux input into lo/hi parts.
* Rename register.
* Combine `QUO_INPUT_{LO,HI}`; rearrange some columns.
* Split `MODULAR_AUX_INPUT` into high and low pieces.
* Remove range_check_error debug output.
* First draft of generating the range checks.
* Remove opcodes for operations that were defined elsewhere.
* Clean up interface to build arithmetic trace.
* Fix "degree too high" bug in DIV by zero.
* Fix constraint_transition usage in recursive compare.
* Fix variable name; use named constant.
* Fix comment values.
* Fix bug in recursive MUL circuit.
* Superficial improvements; remove unnecessary genericity.
* Fix bug in recursive MULMOD circuit.
* Remove debugging noise; expand test.
* Minor comment.
* Enforce assumption in assert.
* Make DIV its own operation.
* Make MOD it's own operation; rename structs; refactor.
* Expand basic test.
* Remove comment.
* Put Stark operations in their own file.
* Test long traces.
* Minor comment.
* Address William's comments.
* Use `const_assert!` instead of `debug_assert!` because Clippy.
* First draft of 256-bit addition.
* Update comment.
* cargo fmt
* Rename addition evaluation file.
* Port ALU logic from SZ.
* Give a name to some magic numbers.
* `addition.rs` -> `add.rs`; fix carry propagation in add; impl sub.
* Clippy.
* Combine hi and lo parts of the output.
* Implement MUL.
* Suppress Clippy's attempt to make my code even harder to read.
* Next draft of MUL.
* Make all limbs (i.e. input and output) 16-bits.
* Tidying.
* Use iterators instead of building arrays.
* Documentation.
* Clippy is wrong; also cargo fmt.
* Un-refactor equality checking, since it was wrong for sub.
* Daniel comments.
* Daniel comments.
* Rename folder 'alu' -> 'arithmetic'.
* Rename file.
* Finish changing name ALU -> Arithmetic Unit.
* Finish removing dependency on array_zip feature.
* Remove operations that will be handled elsewhere.
* Rename var; tidy up.
* Clean up columns; mark places where range-checks need to be done.
* Import all names in 'columns' to reduce verbiage.
* cargo fmt
* Fix aux_in calculation in mul.
* Remove redundant 'allow's; more precise range-check size.
* Document functions.
* Document MUL instruction verification technique.
* Initial tests for ADD.
* Minor test fixes; add test for SUB.
* Fix bugs in generate functions.
* Fix SUB verification; refactor equality verification.
* cargo fmt
* Add test for MUL and fix some bugs.
* Update doc.
* Quiet incorrect clippy error.
* Initial implementation of ADDMOD and MOD.
* Fixes to addmod.
* Update doc.
* Do 1000 random tests instead of just 1.
* Documentation fix.
* Working version of ADDMOD.
* Working version of MOD.
* Name magic number; do multiple MUL tests.
* Add code and test for special case; add some docs.
* Fix spelling mistake.
* Simplify asserts.
* Tidy comment.
* Remove unused module.
* cargo fmt
* Check that output is reduced.
* Add conversion of canonical `i64` to a `Field64`.
* Handle zero modulus within degree constraint.
* cargo fmt
* Fix some comments.
* Check that the top half of the product is zero!
* Start of refactor.
* Refactoring.
* Remove zero and reduction handling from addmod.
* Refactoring; renaming; bug fixes.
* Reuse intermediate calculations across all modular operations; don't negate quot poly unnecessarily.
* Fix bug where last elt of q*m wasn't checked.
* Refactoring.
* Move circuit poly functions to utils.rs.
* Rename ADDMOD stuff to MODULAR.
* Rename module addmod -> modular.
* Handle zero modulus.
* Verify that output is reduced.
* Implement recursive version of modular circuits.
* clippy
* Tidy up i64 -> Field conversion following Jacqui's comments.
* cargo fmt
* Improved documentation.
* Address Jacqui's comments.
* Save some gates by using builder.arithmetic_extension().
* First draft of 256-bit addition.
* Update comment.
* cargo fmt
* Rename addition evaluation file.
* Port ALU logic from SZ.
* Give a name to some magic numbers.
* `addition.rs` -> `add.rs`; fix carry propagation in add; impl sub.
* Clippy.
* Combine hi and lo parts of the output.
* Implement MUL.
* Suppress Clippy's attempt to make my code even harder to read.
* Next draft of MUL.
* Make all limbs (i.e. input and output) 16-bits.
* Tidying.
* Use iterators instead of building arrays.
* Documentation.
* Clippy is wrong; also cargo fmt.
* Un-refactor equality checking, since it was wrong for sub.
* Daniel comments.
* Daniel comments.
* Rename folder 'alu' -> 'arithmetic'.
* Rename file.
* Finish changing name ALU -> Arithmetic Unit.
* Finish removing dependency on array_zip feature.
* Remove operations that will be handled elsewhere.
* Rename var; tidy up.
* Clean up columns; mark places where range-checks need to be done.
* Import all names in 'columns' to reduce verbiage.
* cargo fmt
* Fix aux_in calculation in mul.
* Remove redundant 'allow's; more precise range-check size.
* Document functions.
* Document MUL instruction verification technique.
* Initial tests for ADD.
* Minor test fixes; add test for SUB.
* Fix bugs in generate functions.
* Fix SUB verification; refactor equality verification.
* cargo fmt
* Add test for MUL and fix some bugs.
* Update doc.
* Quiet incorrect clippy error.
* Clean up 'decode.rs'.
* Fold 'decode.rs' into 'arithmetic_stark.rs'.
* Force limb size to divide EVM register size.
* Document range-check warning and fix end value calc.
* Convert `debug_assert!`s into `assert!`s.
* Clean up various kinds of iterator usage.
* Remove unnecessary type spec.
* Document unexpected use of `collect`.
