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exponention gate takes only bits

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This commit is contained in:
Nicholas Ward 2021-07-29 12:58:44 -07:00
parent c5da582f4f
commit e46bd08f00
2 changed files with 9 additions and 35 deletions
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4
src/gadgets/arithmetic.rs
View File

@ -181,11 +181,7 @@ impl<F: Extendable<D>, const D: usize> CircuitBuilder<F, D> {
let gate = ExponentiationGate::new(exp_bits_vec.len());
let gate_index = self.add_gate(gate.clone(), vec![]);
let two = self.constant(F::TWO);
let exponent = reduce_with_powers_recursive(self, &exp_bits_vec[..], two);
self.route(base, Target::wire(gate_index, gate.wire_base()));
self.route(exponent, Target::wire(gate_index, gate.wire_power()));
exp_bits_vec.iter().enumerate().for_each(|(i, bit)| {
self.route(*bit, Target::wire(gate_index, gate.wire_power_bit(i)));
});

40
src/gates/exponentiation.rs
View File

@ -37,23 +37,19 @@ impl<F: Extendable<D>, const D: usize> ExponentiationGate<F, D> {
0
}
pub fn wire_power(&self) -> usize {
1
}
/// The `i`th bit of the exponent, in little-endian order.
pub fn wire_power_bit(&self, i: usize) -> usize {
debug_assert!(i < self.num_power_bits);
2 + i
1 + i
}
pub fn wire_output(&self) -> usize {
2 + self.num_power_bits
1 + self.num_power_bits
}
pub fn wire_intermediate_value(&self, i: usize) -> usize {
debug_assert!(i < self.num_power_bits);
3 + self.num_power_bits + i
2 + self.num_power_bits + i
}
}
@ -64,7 +60,6 @@ impl<F: Extendable<D>, const D: usize> Gate<F, D> for ExponentiationGate<F, D> {
fn eval_unfiltered(&self, vars: EvaluationVars<F, D>) -> Vec<F::Extension> {
let base = vars.local_wires[self.wire_base()];
let power = vars.local_wires[self.wire_power()];
let power_bits: Vec<_> = (0..self.num_power_bits)
.map(|i| vars.local_wires[self.wire_power_bit(i)])
@ -77,9 +72,6 @@ impl<F: Extendable<D>, const D: usize> Gate<F, D> for ExponentiationGate<F, D> {
let mut constraints = Vec::new();
let computed_power = reduce_with_powers(&power_bits, F::Extension::TWO);
constraints.push(power - computed_power);
for i in 0..self.num_power_bits {
let prev_intermediate_value = if i == 0 {
F::Extension::ONE
@ -103,7 +95,6 @@ impl<F: Extendable<D>, const D: usize> Gate<F, D> for ExponentiationGate<F, D> {
fn eval_unfiltered_base(&self, vars: EvaluationVarsBase<F>) -> Vec<F> {
let base = vars.local_wires[self.wire_base()];
let power = vars.local_wires[self.wire_power()];
let power_bits: Vec<_> = (0..self.num_power_bits)
.map(|i| vars.local_wires[self.wire_power_bit(i)])
@ -116,9 +107,6 @@ impl<F: Extendable<D>, const D: usize> Gate<F, D> for ExponentiationGate<F, D> {
let mut constraints = Vec::new();
let computed_power = reduce_with_powers(&power_bits, F::TWO);
constraints.push(power - computed_power);
for i in 0..self.num_power_bits {
let prev_intermediate_value = if i == 0 {
F::ONE
@ -146,7 +134,6 @@ impl<F: Extendable<D>, const D: usize> Gate<F, D> for ExponentiationGate<F, D> {
vars: EvaluationTargets<D>,
) -> Vec<ExtensionTarget<D>> {
let base = vars.local_wires[self.wire_base()];
let power = vars.local_wires[self.wire_power()];
let power_bits: Vec<_> = (0..self.num_power_bits)
.map(|i| vars.local_wires[self.wire_power_bit(i)])
@ -159,11 +146,6 @@ impl<F: Extendable<D>, const D: usize> Gate<F, D> for ExponentiationGate<F, D> {
let mut constraints = Vec::new();
let two = builder.constant(F::TWO);
let computed_power = reduce_with_powers_ext_recursive(builder, &power_bits, two);
let power_diff = builder.sub_extension(power, computed_power);
constraints.push(power_diff);
let one = builder.constant_extension(F::Extension::ONE);
for i in 0..self.num_power_bits {
let prev_intermediate_value = if i == 0 {
@ -214,7 +196,7 @@ impl<F: Extendable<D>, const D: usize> Gate<F, D> for ExponentiationGate<F, D> {
}
fn num_constraints(&self) -> usize {
self.num_power_bits + 2
self.num_power_bits + 1
}
}
@ -230,7 +212,6 @@ impl<F: Extendable<D>, const D: usize> SimpleGenerator<F> for ExponentiationGene
let mut deps = Vec::with_capacity(self.gate.num_power_bits + 2);
deps.push(local_target(self.gate.wire_base()));
deps.push(local_target(self.gate.wire_power()));
for i in 0..self.gate.num_power_bits {
deps.push(local_target(self.gate.wire_power_bit(i)));
}
@ -301,12 +282,11 @@ mod tests {
};
assert_eq!(gate.wire_base(), 0);
assert_eq!(gate.wire_power(), 1);
assert_eq!(gate.wire_power_bit(0), 2);
assert_eq!(gate.wire_power_bit(4), 6);
assert_eq!(gate.wire_output(), 7);
assert_eq!(gate.wire_intermediate_value(0), 8);
assert_eq!(gate.wire_intermediate_value(4), 12);
assert_eq!(gate.wire_power_bit(0), 1);
assert_eq!(gate.wire_power_bit(4), 5);
assert_eq!(gate.wire_output(), 6);
assert_eq!(gate.wire_intermediate_value(0), 7);
assert_eq!(gate.wire_intermediate_value(4), 11);
}
#[test]
@ -332,7 +312,6 @@ mod tests {
let num_power_bits = power_bits.len();
let power_F = F::from_canonical_u64(power);
let power_bits_F: Vec<_> = power_bits
.iter()
.map(|b| F::from_canonical_u64(*b))
@ -340,7 +319,6 @@ mod tests {
let mut v = Vec::new();
v.push(base);
v.push(power_F);
v.extend(power_bits_F.clone());
let mut intermediate_values = Vec::new();