From e46bd08f009c0c43bdd6aac1658f2f2d530c5cf3 Mon Sep 17 00:00:00 2001 From: Nicholas Ward Date: Thu, 29 Jul 2021 12:58:44 -0700 Subject: [PATCH] exponention gate takes only bits --- src/gadgets/arithmetic.rs | 4 ---- src/gates/exponentiation.rs | 40 +++++++++---------------------------- 2 files changed, 9 insertions(+), 35 deletions(-) diff --git a/src/gadgets/arithmetic.rs b/src/gadgets/arithmetic.rs index 5597499d..5974fd05 100644 --- a/src/gadgets/arithmetic.rs +++ b/src/gadgets/arithmetic.rs @@ -181,11 +181,7 @@ impl, const D: usize> CircuitBuilder { let gate = ExponentiationGate::new(exp_bits_vec.len()); let gate_index = self.add_gate(gate.clone(), vec![]); - let two = self.constant(F::TWO); - let exponent = reduce_with_powers_recursive(self, &exp_bits_vec[..], two); - self.route(base, Target::wire(gate_index, gate.wire_base())); - self.route(exponent, Target::wire(gate_index, gate.wire_power())); exp_bits_vec.iter().enumerate().for_each(|(i, bit)| { self.route(*bit, Target::wire(gate_index, gate.wire_power_bit(i))); }); diff --git a/src/gates/exponentiation.rs b/src/gates/exponentiation.rs index 670f5365..d8cf90ea 100644 --- a/src/gates/exponentiation.rs +++ b/src/gates/exponentiation.rs @@ -37,23 +37,19 @@ impl, const D: usize> ExponentiationGate { 0 } - pub fn wire_power(&self) -> usize { - 1 - } - /// The `i`th bit of the exponent, in little-endian order. pub fn wire_power_bit(&self, i: usize) -> usize { debug_assert!(i < self.num_power_bits); - 2 + i + 1 + i } pub fn wire_output(&self) -> usize { - 2 + self.num_power_bits + 1 + self.num_power_bits } pub fn wire_intermediate_value(&self, i: usize) -> usize { debug_assert!(i < self.num_power_bits); - 3 + self.num_power_bits + i + 2 + self.num_power_bits + i } } @@ -64,7 +60,6 @@ impl, const D: usize> Gate for ExponentiationGate { fn eval_unfiltered(&self, vars: EvaluationVars) -> Vec { let base = vars.local_wires[self.wire_base()]; - let power = vars.local_wires[self.wire_power()]; let power_bits: Vec<_> = (0..self.num_power_bits) .map(|i| vars.local_wires[self.wire_power_bit(i)]) @@ -77,9 +72,6 @@ impl, const D: usize> Gate for ExponentiationGate { let mut constraints = Vec::new(); - let computed_power = reduce_with_powers(&power_bits, F::Extension::TWO); - constraints.push(power - computed_power); - for i in 0..self.num_power_bits { let prev_intermediate_value = if i == 0 { F::Extension::ONE @@ -103,7 +95,6 @@ impl, const D: usize> Gate for ExponentiationGate { fn eval_unfiltered_base(&self, vars: EvaluationVarsBase) -> Vec { let base = vars.local_wires[self.wire_base()]; - let power = vars.local_wires[self.wire_power()]; let power_bits: Vec<_> = (0..self.num_power_bits) .map(|i| vars.local_wires[self.wire_power_bit(i)]) @@ -116,9 +107,6 @@ impl, const D: usize> Gate for ExponentiationGate { let mut constraints = Vec::new(); - let computed_power = reduce_with_powers(&power_bits, F::TWO); - constraints.push(power - computed_power); - for i in 0..self.num_power_bits { let prev_intermediate_value = if i == 0 { F::ONE @@ -146,7 +134,6 @@ impl, const D: usize> Gate for ExponentiationGate { vars: EvaluationTargets, ) -> Vec> { let base = vars.local_wires[self.wire_base()]; - let power = vars.local_wires[self.wire_power()]; let power_bits: Vec<_> = (0..self.num_power_bits) .map(|i| vars.local_wires[self.wire_power_bit(i)]) @@ -159,11 +146,6 @@ impl, const D: usize> Gate for ExponentiationGate { let mut constraints = Vec::new(); - let two = builder.constant(F::TWO); - let computed_power = reduce_with_powers_ext_recursive(builder, &power_bits, two); - let power_diff = builder.sub_extension(power, computed_power); - constraints.push(power_diff); - let one = builder.constant_extension(F::Extension::ONE); for i in 0..self.num_power_bits { let prev_intermediate_value = if i == 0 { @@ -214,7 +196,7 @@ impl, const D: usize> Gate for ExponentiationGate { } fn num_constraints(&self) -> usize { - self.num_power_bits + 2 + self.num_power_bits + 1 } } @@ -230,7 +212,6 @@ impl, const D: usize> SimpleGenerator for ExponentiationGene let mut deps = Vec::with_capacity(self.gate.num_power_bits + 2); deps.push(local_target(self.gate.wire_base())); - deps.push(local_target(self.gate.wire_power())); for i in 0..self.gate.num_power_bits { deps.push(local_target(self.gate.wire_power_bit(i))); } @@ -301,12 +282,11 @@ mod tests { }; assert_eq!(gate.wire_base(), 0); - assert_eq!(gate.wire_power(), 1); - assert_eq!(gate.wire_power_bit(0), 2); - assert_eq!(gate.wire_power_bit(4), 6); - assert_eq!(gate.wire_output(), 7); - assert_eq!(gate.wire_intermediate_value(0), 8); - assert_eq!(gate.wire_intermediate_value(4), 12); + assert_eq!(gate.wire_power_bit(0), 1); + assert_eq!(gate.wire_power_bit(4), 5); + assert_eq!(gate.wire_output(), 6); + assert_eq!(gate.wire_intermediate_value(0), 7); + assert_eq!(gate.wire_intermediate_value(4), 11); } #[test] @@ -332,7 +312,6 @@ mod tests { let num_power_bits = power_bits.len(); - let power_F = F::from_canonical_u64(power); let power_bits_F: Vec<_> = power_bits .iter() .map(|b| F::from_canonical_u64(*b)) @@ -340,7 +319,6 @@ mod tests { let mut v = Vec::new(); v.push(base); - v.push(power_F); v.extend(power_bits_F.clone()); let mut intermediate_values = Vec::new();