2022-06-29 16:23:44 -07:00
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use std::borrow::{Borrow, BorrowMut};
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2022-09-22 18:09:23 -07:00
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use std::iter::repeat;
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2022-05-18 09:22:58 +02:00
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use std::marker::PhantomData;
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2022-06-23 14:36:14 -07:00
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use itertools::Itertools;
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2022-06-27 07:18:21 -07:00
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use plonky2::field::extension::{Extendable, FieldExtension};
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2022-06-27 15:07:52 -07:00
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use plonky2::field::packed::PackedField;
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2022-06-27 12:24:09 -07:00
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use plonky2::field::types::Field;
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2022-05-18 09:22:58 +02:00
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use plonky2::hash::hash_types::RichField;
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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use crate::all_stark::Table;
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2022-05-18 09:22:58 +02:00
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use crate::constraint_consumer::{ConstraintConsumer, RecursiveConstraintConsumer};
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2022-06-29 16:23:44 -07:00
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use crate::cpu::columns::{CpuColumnsView, COL_MAP, NUM_CPU_COLUMNS};
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2022-12-15 13:56:48 -08:00
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use crate::cpu::membus::NUM_GP_CHANNELS;
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2022-09-10 13:20:30 -07:00
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use crate::cpu::{
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2023-07-21 10:55:09 +01:00
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bootstrap_kernel, contextops, control_flow, decode, dup_swap, gas, jumps, membus, memio,
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modfp254, pc, push0, shift, simple_logic, stack, stack_bounds, syscalls_exceptions,
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2022-09-10 13:20:30 -07:00
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};
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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use crate::cross_table_lookup::{Column, TableWithColumns};
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2022-09-22 18:09:23 -07:00
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use crate::memory::segments::Segment;
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use crate::memory::{NUM_CHANNELS, VALUE_LIMBS};
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2022-05-18 09:22:58 +02:00
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use crate::stark::Stark;
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use crate::vars::{StarkEvaluationTargets, StarkEvaluationVars};
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2022-12-03 11:21:31 -08:00
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pub fn ctl_data_keccak_sponge<F: Field>() -> Vec<Column<F>> {
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2022-09-22 18:09:23 -07:00
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// When executing KECCAK_GENERAL, the GP memory channels are used as follows:
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// GP channel 0: stack[-1] = context
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// GP channel 1: stack[-2] = segment
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2022-12-03 11:21:31 -08:00
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// GP channel 2: stack[-3] = virt
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// GP channel 3: stack[-4] = len
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// GP channel 4: pushed = outputs
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2022-09-22 18:09:23 -07:00
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let context = Column::single(COL_MAP.mem_channels[0].value[0]);
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let segment = Column::single(COL_MAP.mem_channels[1].value[0]);
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let virt = Column::single(COL_MAP.mem_channels[2].value[0]);
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2022-12-03 11:21:31 -08:00
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let len = Column::single(COL_MAP.mem_channels[3].value[0]);
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2022-08-14 16:36:07 -07:00
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let num_channels = F::from_canonical_usize(NUM_CHANNELS);
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2022-12-03 11:21:31 -08:00
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let timestamp = Column::linear_combination([(COL_MAP.clock, num_channels)]);
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2022-08-14 16:36:07 -07:00
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2022-12-03 11:21:31 -08:00
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let mut cols = vec![context, segment, virt, len, timestamp];
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2022-12-15 13:56:48 -08:00
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cols.extend(COL_MAP.mem_channels[4].value.map(Column::single));
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2022-12-03 11:21:31 -08:00
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cols
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2022-06-21 10:28:44 -07:00
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}
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2022-12-03 11:21:31 -08:00
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pub fn ctl_filter_keccak_sponge<F: Field>() -> Column<F> {
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Column::single(COL_MAP.is_keccak_sponge)
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2022-08-14 16:36:07 -07:00
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}
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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/// Create the vector of Columns corresponding to the two inputs and
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/// one output of a binary operation.
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2023-09-14 10:36:48 -04:00
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fn ctl_data_binops<F: Field>() -> Vec<Column<F>> {
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let mut res = Column::singles(COL_MAP.mem_channels[0].value).collect_vec();
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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res.extend(Column::singles(COL_MAP.mem_channels[1].value));
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res.extend(Column::singles(
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COL_MAP.mem_channels[NUM_GP_CHANNELS - 1].value,
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));
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res
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}
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/// Create the vector of Columns corresponding to the three inputs and
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2023-08-09 09:17:06 -04:00
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/// one output of a ternary operation. By default, ternary operations use
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/// the first three memory channels, and the last one for the result (binary
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/// operations do not use the third inputs).
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///
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/// Shift operations are different, as they are simulated with `MUL` or `DIV`
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/// on the arithmetic side. We first convert the shift into the multiplicand
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/// (in case of `SHL`) or the divisor (in case of `SHR`), making the first memory
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/// channel not directly usable. We overcome this by adding an offset of 1 in
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/// case of shift operations, which will skip the first memory channel and use the
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/// next three as ternary inputs. Because both `MUL` and `DIV` are binary operations,
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/// the last memory channel used for the inputs will be safely ignored.
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2023-09-14 10:36:48 -04:00
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fn ctl_data_ternops<F: Field>(is_shift: bool) -> Vec<Column<F>> {
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2023-08-09 09:17:06 -04:00
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let offset = is_shift as usize;
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2023-09-14 10:36:48 -04:00
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let mut res = Column::singles(COL_MAP.mem_channels[offset].value).collect_vec();
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2023-08-09 09:17:06 -04:00
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res.extend(Column::singles(COL_MAP.mem_channels[offset + 1].value));
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res.extend(Column::singles(COL_MAP.mem_channels[offset + 2].value));
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2022-12-15 13:56:48 -08:00
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res.extend(Column::singles(
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COL_MAP.mem_channels[NUM_GP_CHANNELS - 1].value,
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));
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2022-06-21 10:28:44 -07:00
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res
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}
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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pub fn ctl_data_logic<F: Field>() -> Vec<Column<F>> {
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2023-08-11 10:21:11 -04:00
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// Instead of taking single columns, we reconstruct the entire opcode value directly.
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2023-08-11 09:23:58 -04:00
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let mut res = vec![Column::le_bits(COL_MAP.opcode_bits)];
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2023-09-14 10:36:48 -04:00
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res.extend(ctl_data_binops());
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2023-08-11 09:23:58 -04:00
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res
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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}
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2022-06-21 10:28:44 -07:00
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pub fn ctl_filter_logic<F: Field>() -> Column<F> {
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2023-08-11 10:17:45 -04:00
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Column::single(COL_MAP.op.logic_op)
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2022-06-21 10:28:44 -07:00
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}
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2023-08-09 09:17:06 -04:00
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pub fn ctl_arithmetic_base_rows<F: Field>() -> TableWithColumns<F> {
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2023-09-14 10:36:48 -04:00
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// Instead of taking single columns, we reconstruct the entire opcode value directly.
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let mut columns = vec![Column::le_bits(COL_MAP.opcode_bits)];
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columns.extend(ctl_data_ternops(false));
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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// Create the CPU Table whose columns are those with the three
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// inputs and one output of the ternary operations listed in `ops`
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// (also `ops` is used as the operation filter). The list of
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// operations includes binary operations which will simply ignore
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// the third input.
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2023-08-09 09:17:06 -04:00
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TableWithColumns::new(
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Table::Cpu,
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2023-09-14 10:36:48 -04:00
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columns,
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Some(Column::sum([
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COL_MAP.op.binary_op,
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COL_MAP.op.fp254_op,
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COL_MAP.op.ternary_op,
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])),
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2023-08-09 09:17:06 -04:00
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)
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}
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pub fn ctl_arithmetic_shift_rows<F: Field>() -> TableWithColumns<F> {
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2023-09-14 10:36:48 -04:00
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// Instead of taking single columns, we reconstruct the entire opcode value directly.
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let mut columns = vec![Column::le_bits(COL_MAP.opcode_bits)];
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columns.extend(ctl_data_ternops(true));
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2023-08-09 09:17:06 -04:00
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// Create the CPU Table whose columns are those with the three
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// inputs and one output of the ternary operations listed in `ops`
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// (also `ops` is used as the operation filter). The list of
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// operations includes binary operations which will simply ignore
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// the third input.
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2023-09-14 10:36:48 -04:00
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TableWithColumns::new(Table::Cpu, columns, Some(Column::single(COL_MAP.op.shift)))
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Cross-table lookup for arithmetic stark (#905)
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
2023-05-11 03:29:06 +10:00
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}
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2023-09-12 14:45:37 -04:00
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pub fn ctl_data_byte_packing<F: Field>() -> Vec<Column<F>> {
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ctl_data_keccak_sponge()
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}
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pub fn ctl_filter_byte_packing<F: Field>() -> Column<F> {
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Column::single(COL_MAP.op.mload_32bytes)
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}
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pub fn ctl_data_byte_unpacking<F: Field>() -> Vec<Column<F>> {
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// When executing MSTORE_32BYTES, the GP memory channels are used as follows:
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// GP channel 0: stack[-1] = context
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// GP channel 1: stack[-2] = segment
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// GP channel 2: stack[-3] = virt
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// GP channel 3: stack[-4] = val
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// GP channel 4: stack[-5] = len
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let context = Column::single(COL_MAP.mem_channels[0].value[0]);
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let segment = Column::single(COL_MAP.mem_channels[1].value[0]);
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let virt = Column::single(COL_MAP.mem_channels[2].value[0]);
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let val = Column::singles(COL_MAP.mem_channels[3].value);
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let len = Column::single(COL_MAP.mem_channels[4].value[0]);
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let num_channels = F::from_canonical_usize(NUM_CHANNELS);
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let timestamp = Column::linear_combination([(COL_MAP.clock, num_channels)]);
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let mut res = vec![context, segment, virt, len, timestamp];
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res.extend(val);
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res
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}
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pub fn ctl_filter_byte_unpacking<F: Field>() -> Column<F> {
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Column::single(COL_MAP.op.mstore_32bytes)
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}
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2022-09-22 18:09:23 -07:00
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pub const MEM_CODE_CHANNEL_IDX: usize = 0;
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pub const MEM_GP_CHANNELS_IDX_START: usize = MEM_CODE_CHANNEL_IDX + 1;
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/// Make the time/channel column for memory lookups.
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fn mem_time_and_channel<F: Field>(channel: usize) -> Column<F> {
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let scalar = F::from_canonical_usize(NUM_CHANNELS);
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let addend = F::from_canonical_usize(channel);
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Column::linear_combination_with_constant([(COL_MAP.clock, scalar)], addend)
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}
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pub fn ctl_data_code_memory<F: Field>() -> Vec<Column<F>> {
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let mut cols = vec![
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Column::constant(F::ONE), // is_read
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Column::single(COL_MAP.code_context), // addr_context
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Column::constant(F::from_canonical_u64(Segment::Code as u64)), // addr_segment
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Column::single(COL_MAP.program_counter), // addr_virtual
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];
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// Low limb of the value matches the opcode bits
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cols.push(Column::le_bits(COL_MAP.opcode_bits));
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// High limbs of the value are all zero.
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cols.extend(repeat(Column::constant(F::ZERO)).take(VALUE_LIMBS - 1));
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cols.push(mem_time_and_channel(MEM_CODE_CHANNEL_IDX));
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cols
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}
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pub fn ctl_data_gp_memory<F: Field>(channel: usize) -> Vec<Column<F>> {
|
2022-08-26 22:05:16 -07:00
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let channel_map = COL_MAP.mem_channels[channel];
|
2022-09-22 18:09:23 -07:00
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let mut cols: Vec<_> = Column::singles([
|
2022-08-26 22:05:16 -07:00
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channel_map.is_read,
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channel_map.addr_context,
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channel_map.addr_segment,
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channel_map.addr_virtual,
|
2022-06-23 14:36:14 -07:00
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])
|
2022-09-22 18:09:23 -07:00
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.collect();
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|
2022-08-26 22:05:16 -07:00
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cols.extend(Column::singles(channel_map.value));
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2022-07-07 09:27:50 -07:00
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|
2022-09-22 18:09:23 -07:00
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cols.push(mem_time_and_channel(MEM_GP_CHANNELS_IDX_START + channel));
|
2022-07-07 09:52:38 -07:00
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|
2022-06-23 14:36:14 -07:00
|
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|
cols
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|
}
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|
2022-09-22 18:09:23 -07:00
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pub fn ctl_filter_code_memory<F: Field>() -> Column<F> {
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2023-08-11 12:07:17 -04:00
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Column::sum(COL_MAP.op.iter())
|
2022-09-22 18:09:23 -07:00
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}
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|
pub fn ctl_filter_gp_memory<F: Field>(channel: usize) -> Column<F> {
|
2022-08-26 22:05:16 -07:00
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Column::single(COL_MAP.mem_channels[channel].used)
|
2022-06-23 14:36:14 -07:00
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|
}
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|
2022-07-04 18:10:03 -07:00
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|
#[derive(Copy, Clone, Default)]
|
2022-05-18 09:22:58 +02:00
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|
pub struct CpuStark<F, const D: usize> {
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|
|
pub f: PhantomData<F>,
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|
|
}
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|
2022-06-03 19:24:47 -07:00
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impl<F: RichField, const D: usize> CpuStark<F, D> {
|
2022-12-03 12:02:51 -08:00
|
|
|
// TODO: Remove?
|
2022-06-29 16:23:44 -07:00
|
|
|
pub fn generate(&self, local_values: &mut [F; NUM_CPU_COLUMNS]) {
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|
|
|
let local_values: &mut CpuColumnsView<_> = local_values.borrow_mut();
|
2022-06-03 19:24:47 -07:00
|
|
|
decode::generate(local_values);
|
2022-09-22 18:09:23 -07:00
|
|
|
membus::generate(local_values);
|
2022-06-03 19:24:47 -07:00
|
|
|
}
|
|
|
|
|
}
|
|
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|
|
|
2022-05-18 09:22:58 +02:00
|
|
|
impl<F: RichField + Extendable<D>, const D: usize> Stark<F, D> for CpuStark<F, D> {
|
2022-06-29 16:23:44 -07:00
|
|
|
const COLUMNS: usize = NUM_CPU_COLUMNS;
|
2022-05-18 09:22:58 +02:00
|
|
|
|
|
|
|
|
fn eval_packed_generic<FE, P, const D2: usize>(
|
|
|
|
|
&self,
|
2022-08-25 12:24:22 -07:00
|
|
|
vars: StarkEvaluationVars<FE, P, { Self::COLUMNS }>,
|
2022-12-02 22:47:07 -08:00
|
|
|
yield_constr: &mut ConstraintConsumer<P>,
|
2022-05-18 09:22:58 +02:00
|
|
|
) where
|
|
|
|
|
FE: FieldExtension<D2, BaseField = F>,
|
|
|
|
|
P: PackedField<Scalar = FE>,
|
|
|
|
|
{
|
2022-12-02 14:49:32 -08:00
|
|
|
let local_values = vars.local_values.borrow();
|
|
|
|
|
let next_values = vars.next_values.borrow();
|
2022-12-02 22:47:07 -08:00
|
|
|
bootstrap_kernel::eval_bootstrap_kernel(vars, yield_constr);
|
2022-12-11 10:59:14 -08:00
|
|
|
contextops::eval_packed(local_values, next_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
control_flow::eval_packed_generic(local_values, next_values, yield_constr);
|
2023-04-07 17:06:57 -04:00
|
|
|
decode::eval_packed_generic(local_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
dup_swap::eval_packed(local_values, yield_constr);
|
2023-02-14 22:30:19 -08:00
|
|
|
gas::eval_packed(local_values, next_values, yield_constr);
|
2022-12-11 11:08:33 -08:00
|
|
|
jumps::eval_packed(local_values, next_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
membus::eval_packed(local_values, yield_constr);
|
2023-09-15 00:51:02 +01:00
|
|
|
memio::eval_packed(local_values, next_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
modfp254::eval_packed(local_values, yield_constr);
|
2022-12-11 10:41:32 -08:00
|
|
|
pc::eval_packed(local_values, yield_constr);
|
2023-06-13 13:29:30 -07:00
|
|
|
push0::eval_packed(local_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
shift::eval_packed(local_values, yield_constr);
|
2023-08-28 16:32:04 -04:00
|
|
|
simple_logic::eval_packed(local_values, next_values, yield_constr);
|
|
|
|
|
stack::eval_packed(local_values, next_values, yield_constr);
|
2023-04-11 15:13:55 -04:00
|
|
|
stack_bounds::eval_packed(local_values, yield_constr);
|
2023-07-21 10:55:09 +01:00
|
|
|
syscalls_exceptions::eval_packed(local_values, next_values, yield_constr);
|
2022-05-18 09:22:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
fn eval_ext_circuit(
|
|
|
|
|
&self,
|
2022-06-03 19:24:47 -07:00
|
|
|
builder: &mut plonky2::plonk::circuit_builder::CircuitBuilder<F, D>,
|
2022-08-25 12:24:22 -07:00
|
|
|
vars: StarkEvaluationTargets<D, { Self::COLUMNS }>,
|
2022-12-02 22:47:07 -08:00
|
|
|
yield_constr: &mut RecursiveConstraintConsumer<F, D>,
|
2022-05-18 09:22:58 +02:00
|
|
|
) {
|
2022-06-29 16:23:44 -07:00
|
|
|
let local_values = vars.local_values.borrow();
|
2022-07-28 04:36:33 +10:00
|
|
|
let next_values = vars.next_values.borrow();
|
2022-12-02 22:47:07 -08:00
|
|
|
bootstrap_kernel::eval_bootstrap_kernel_circuit(builder, vars, yield_constr);
|
2022-12-11 10:59:14 -08:00
|
|
|
contextops::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
control_flow::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
2023-04-07 17:06:57 -04:00
|
|
|
decode::eval_ext_circuit(builder, local_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
dup_swap::eval_ext_circuit(builder, local_values, yield_constr);
|
2023-02-14 22:30:19 -08:00
|
|
|
gas::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
2022-12-11 11:08:33 -08:00
|
|
|
jumps::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
membus::eval_ext_circuit(builder, local_values, yield_constr);
|
2023-09-15 00:51:02 +01:00
|
|
|
memio::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
modfp254::eval_ext_circuit(builder, local_values, yield_constr);
|
2022-12-11 10:41:32 -08:00
|
|
|
pc::eval_ext_circuit(builder, local_values, yield_constr);
|
2023-06-13 13:29:30 -07:00
|
|
|
push0::eval_ext_circuit(builder, local_values, yield_constr);
|
2022-12-02 22:47:07 -08:00
|
|
|
shift::eval_ext_circuit(builder, local_values, yield_constr);
|
2023-08-28 16:32:04 -04:00
|
|
|
simple_logic::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
|
|
|
|
stack::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
2023-04-11 15:13:55 -04:00
|
|
|
stack_bounds::eval_ext_circuit(builder, local_values, yield_constr);
|
2023-07-21 10:55:09 +01:00
|
|
|
syscalls_exceptions::eval_ext_circuit(builder, local_values, next_values, yield_constr);
|
2022-05-18 09:22:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
fn constraint_degree(&self) -> usize {
|
|
|
|
|
3
|
|
|
|
|
}
|
|
|
|
|
}
|
2022-05-19 11:10:10 +02:00
|
|
|
|
|
|
|
|
#[cfg(test)]
|
|
|
|
|
mod tests {
|
|
|
|
|
use anyhow::Result;
|
|
|
|
|
use plonky2::plonk::config::{GenericConfig, PoseidonGoldilocksConfig};
|
|
|
|
|
|
|
|
|
|
use crate::cpu::cpu_stark::CpuStark;
|
|
|
|
|
use crate::stark_testing::{test_stark_circuit_constraints, test_stark_low_degree};
|
|
|
|
|
|
|
|
|
|
#[test]
|
2022-05-20 08:34:25 +02:00
|
|
|
fn test_stark_degree() -> Result<()> {
|
2022-05-19 11:10:10 +02:00
|
|
|
const D: usize = 2;
|
|
|
|
|
type C = PoseidonGoldilocksConfig;
|
|
|
|
|
type F = <C as GenericConfig<D>>::F;
|
|
|
|
|
type S = CpuStark<F, D>;
|
|
|
|
|
|
|
|
|
|
let stark = S {
|
|
|
|
|
f: Default::default(),
|
|
|
|
|
};
|
2022-05-20 08:34:25 +02:00
|
|
|
test_stark_low_degree(stark)
|
2022-05-19 11:10:10 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#[test]
|
|
|
|
|
fn test_stark_circuit() -> Result<()> {
|
|
|
|
|
const D: usize = 2;
|
|
|
|
|
type C = PoseidonGoldilocksConfig;
|
|
|
|
|
type F = <C as GenericConfig<D>>::F;
|
|
|
|
|
type S = CpuStark<F, D>;
|
|
|
|
|
|
|
|
|
|
let stark = S {
|
|
|
|
|
f: Default::default(),
|
|
|
|
|
};
|
|
|
|
|
test_stark_circuit_constraints::<F, C, S, D>(stark)
|
|
|
|
|
}
|
|
|
|
|
}
|