126 lines
4.1 KiB
Nim
126 lines
4.1 KiB
Nim
# beacon_chain
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# Copyright (c) 2018 Status Research & Development GmbH
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# Licensed and distributed under either of
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# * MIT license (license terms in the root directory or at https://opensource.org/licenses/MIT).
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# * Apache v2 license (license terms in the root directory or at https://www.apache.org/licenses/LICENSE-2.0).
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# at your option. This file may not be copied, modified, or distributed except according to those terms.
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# Cpu Name
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# -------------------------------------------------------
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{.passC:"-std=gnu99".} # TODO may conflict with milagro "-std=c99"
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proc cpuID(eaxi, ecxi: int32): tuple[eax, ebx, ecx, edx: int32] =
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when defined(vcc):
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proc cpuidVcc(cpuInfo: ptr int32; functionID: int32)
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{.importc: "__cpuidex", header: "intrin.h".}
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cpuidVcc(addr result.eax, eaxi, ecxi)
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else:
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var (eaxr, ebxr, ecxr, edxr) = (0'i32, 0'i32, 0'i32, 0'i32)
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asm """
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cpuid
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:"=a"(`eaxr`), "=b"(`ebxr`), "=c"(`ecxr`), "=d"(`edxr`)
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:"a"(`eaxi`), "c"(`ecxi`)"""
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(eaxr, ebxr, ecxr, edxr)
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proc cpuName*(): string =
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var leaves {.global.} = cast[array[48, char]]([
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cpuID(eaxi = 0x80000002'i32, ecxi = 0),
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cpuID(eaxi = 0x80000003'i32, ecxi = 0),
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cpuID(eaxi = 0x80000004'i32, ecxi = 0)])
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result = $cast[cstring](addr leaves[0])
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# Counting cycles
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# -------------------------------------------------------
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# From Linux
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#
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# The RDTSC instruction is not ordered relative to memory
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# access. The Intel SDM and the AMD APM are both vague on this
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# point, but empirically an RDTSC instruction can be
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# speculatively executed before prior loads. An RDTSC
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# immediately after an appropriate barrier appears to be
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# ordered as a normal load, that is, it provides the same
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# ordering guarantees as reading from a global memory location
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# that some other imaginary CPU is updating continuously with a
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# time stamp.
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#
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# From Intel SDM
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# https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-32-ia-64-benchmark-code-execution-paper.pdf
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proc getTicks*(): int64 {.inline.} =
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when defined(vcc):
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proc rdtsc(): int64 {.sideeffect, importc: "__rdtsc", header: "<intrin.h>".}
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proc lfence() {.importc: "__mm_lfence", header: "<intrin.h>".}
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lfence()
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return rdtsc()
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else:
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when defined(amd64):
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var lo, hi: int64
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# TODO: Provide a compile-time flag for RDTSCP support
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# and use it instead of lfence + RDTSC
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{.emit: """asm volatile(
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"lfence\n"
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"rdtsc\n"
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: "=a"(`lo`), "=d"(`hi`)
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:
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: "memory"
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);""".}
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return (hi shl 32) or lo
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else: # 32-bit x86
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# TODO: Provide a compile-time flag for RDTSCP support
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# and use it instead of lfence + RDTSC
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{.emit: """asm volatile(
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"lfence\n"
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"rdtsc\n"
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: "=a"(`result`)
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:
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: "memory"
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);""".}
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# Sanity check
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# -------------------------------------------------------
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when isMainModule:
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import std/[times, monotimes, math, volatile, os]
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block: # CpuName
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echo "Your CPU is: "
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echo " ", cpuName()
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block: # Cycle Count
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echo "The cost of an int64 modulo operation on your platform is:"
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# Dealing with compiler optimization on microbenchmarks is hard
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{.pragma: volatile, codegenDecl: "volatile $# $#".}
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proc modNtimes(a, b: int64, N: int) {.noinline.} =
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var c{.volatile.}: int64
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for i in 0 ..< N:
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c.addr.volatileStore(a.unsafeAddr.volatileLoad() mod b.unsafeAddr.volatileLoad())
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let a {.volatile.} = 1000003'i64 # a prime number
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let b {.volatile.} = 10007'i64 # another prime number
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let N {.volatile.} = 3_000_000
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let startMono = getMonoTime()
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let startCycles = getTicks()
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modNtimes(a, b, N)
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let stopCycles = getTicks()
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let stopMono = getMonoTime()
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let elapsedMono = inNanoseconds(stopMono - startMono)
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let elapsedCycles = stopCycles - startCycles
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let timerResolutionGHz = round(elapsedCycles.float32 / elapsedMono.float32, 3)
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echo " ", (elapsedCycles) div N, " cycles"
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echo " ", (elapsedMono) div N, " ns/iter"
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echo " ", timerResolutionGHz, " GHz (timer resolution)"
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block: # CPU Frequency
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discard # TODO, surprisingly this is very complex
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