Cpu architecture optimization documentation (#2483)
* x86 features * Update docs/cpu_features.md [skip CI] Co-authored-by: tersec <tersec@users.noreply.github.com> * Update docs/cpu_features.md [skip CI] Co-authored-by: tersec <tersec@users.noreply.github.com> * less space [skip CI] * Add ARMv8 [skip ci] Co-authored-by: tersec <tersec@users.noreply.github.com>
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Mamy Ratsimbazafy
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# CPU Features for Nimbus
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This document describes the CPU-specific features and compilation flags that significantly improves Nimbus performance.
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We focus on x86-64 and ARMv8 (64 bits).
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Given that the major bottleneck of Nimbus is big integer for cryptography, 64-bit architecture improves elliptic curve cryptography processing by ~2x over 32 bits since we can divide the number of low-level assembly operations by half.
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_Note: SHA256 isn't improved by 64-bit since it uses 32-bit operations by design_
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The major bottlenecks that can be improved by CPU specific instructions are:
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- Elliptic curve cryptography for BLS12-381
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- SHA256 hashing
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## x86
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### SSSE3 (Supplemental SSE3)
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Intel: Core 2, 2006\
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AMD: Bulldozer, 2011\
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Flag: `-mssse3`
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Configuration: https://github.com/supranational/blst/blob/v0.3.4/build/assembly.S#L3-L6
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SSSE3 improves SHA256 computations. SHA256 is used **recursively** to hash all consensus objects and to build a merkle tree.
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Thanks to caching, SHA256 computation speed is mostly relevant only when receiving new blocks and attestations from the network, but state transitions do not depend on it (unlike a naive spec implementation).
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**SSSE3 must not be confused with SSE3 from Pentium 3 (2004) and Athlon 64 (2005)**
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```
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git clone https://github.com/status-im/nim-blscurve
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cd nim-blscurve
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git submodule update --init
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nim c -r -d:danger --passC:"-D__BLST_PORTABLE__" --outdir:build benchmarks/bench_sha256.nim
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nim c -r -d:danger --outdir:build benchmarks/bench_sha256.nim
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```
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Due to tree hashing, hashing 32 bytes is the most important benchmark.
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**Without SSSE3**
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```
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Backend: BLST, mode: 64-bit
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==================================================================================
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SHA256 - 32B - BLST 4524886.878 ops/s 221 ns/op 660 cycles
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SHA256 - 128B - BLST 1776198.934 ops/s 563 ns/op 1689 cycles
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SHA256 - 5MB - BLST 70.723 ops/s 14139678 ns/op 42419720 cycles
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```
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**With SSSE3**
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```
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Backend: BLST, mode: 64-bit
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==================================================================================
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SHA256 - 32B - BLST 5376344.086 ops/s 186 ns/op 555 cycles
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SHA256 - 128B - BLST 2183406.114 ops/s 458 ns/op 1376 cycles
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SHA256 - 5MB - BLST 87.142 ops/s 11475557 ns/op 34427254 cycles
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```
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### BMI2 & ADX
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Intel: Broadwell, 2015\
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AMD: Ryzen, 2017\
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Configuration: https://github.com/supranational/blst/blob/v0.3.4/build/assembly.S#L18
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The MULX instruction (BMI2), ADCX and ADOX (ADX) significantly improves big integer multiplication and squaring.
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The speedup is about 20~25% depending on the custom assembly implementation.
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All CPUs that support ADX support BMI2.
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```
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git clone https://github.com/status-im/nim-blscurve
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cd nim-blscurve
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git submodule update --init
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nim c -r -d:danger --hints:off --warnings:off --verbosity:0 --outdir:build benchmarks/bls_signature.nim
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nim c -r -d:danger --passC:"-mbmi2 -madx" --hints:off --warnings:off --verbosity:0 --outdir:build benchmarks/bls_signature.nim
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```
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**Verification** is the bottleneck as it must be done for each block and attestation or aggregate received
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and verifying a block requires verifying up to 6 signatures (block proposer, RANDAO, aggregate verifification of attestations, proposer slashings, attester slashings, voluntary exits).
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**Signing** can become a bottleneck when a node has many validators.
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**Without BMI2 & ADX**
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```
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Backend: BLST, mode: 64-bit
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=============================================================================================================
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BLS signature 1960.023 ops/s 510198 ns/op 1530624 cycles
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BLS verification 743.122 ops/s 1345674 ns/op 4037105 cycles
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BLS agg verif of 1 msg by 128 pubkeys 704.634 ops/s 1419176 ns/op 4257591 cycles
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BLS verif of 6 msgs by 6 pubkeys 120.588 ops/s 8292683 ns/op 24878257 cycles
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Serial batch verify 6 msgs by 6 pubkeys (with blinding) 218.027 ops/s 4586595 ns/op 13759932 cycles
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```
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**With BMI2 & ADX**
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```
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Backend: BLST, mode: 64-bit
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=============================================================================================================
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BLS signature 2550.084 ops/s 392144 ns/op 1176454 cycles
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BLS verification 930.081 ops/s 1075175 ns/op 3225589 cycles
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BLS agg verif of 1 msg by 128 pubkeys 878.672 ops/s 1138081 ns/op 3414286 cycles
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BLS verif of 6 msgs by 6 pubkeys 154.833 ops/s 6458588 ns/op 19376076 cycles
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Serial batch verify 6 msgs by 6 pubkeys (with blinding) 282.562 ops/s 3539046 ns/op 10617328 cycles
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```
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### SHA-NI
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The hardware SHA instructions has NOT been available in Intel consumer hardware until 2021.
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AMD has made it available in Zen architecture since 2017.
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Intel:
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- Rocket Lake (2021)
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- Ice Lake (low-power laptops 2018)
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- Goldmont (Apollo Lake Pentiums & Celerons 2016, Denverton Atoms 2017)
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AMD: Ryzen, 2017\
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Flag: `-msha`
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Configuration: https://github.com/supranational/blst/blob/v0.3.4/src/sha256.h#L11-L12
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On Ryzen, **hardware SHA is 4X faster** than when using SIMD instructions (Table 1, p14).
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- SoK: A Performance Evaluation of Cryptographic InstructionSets on Modern Architectures\
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Armando Faz-Hernández, Julio López, Ana Karina D. S. de Oliveira, 2018\
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https://www.lasca.ic.unicamp.br/media/publications/p9-faz-hernandez.pdf
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## ARM
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32-bit ARM (ARMv6) has a multiplication instruction 32x32 -> 64 called UMULL.
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Unfortunately, 64-bit ARM (ARMv8) unlike x86-64 doesn't have a single 64x64 -> 128 multiplication instruction. MUL and UMULH instruction needs to be used for extended precision multiplication.
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- Multiprecision Multiplication on ARMv8\
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Zhe Liu, Kimmo Jarvinenadl, Weiqiang Liu, Hwajeong Seo\
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http://arith24.arithsymposium.org/slides/s2-liu.pdf
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Concretely, this means that ARMv8 CPUs are impaired compared to x86-64 at equivalent frequency for big integers and cryptography (for example Apple M1).
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### Cryptographic extensions
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Except for Raspberry Pi, ARMv8 processors support the crypto extensions which include hardware implementation of SHA256.
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This is detected via
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- `__ARM_FEATURE_CRYPTO` https://github.com/supranational/blst/blob/v0.3.4/src/sha256.h#L14-L15
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The compilation flag should be either
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- `-mfpu=crypto-neon-fp-armv8`
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- or `-march=armv8-a+crypto`
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The speedup is expected to be 2x faster than without.\
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https://patchwork.kernel.org/project/linux-arm-kernel/patch/20150316154835.GA31336@google.com/
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