/* * How to setup clock using clock driver functions: * * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. * * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. * * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. * * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. * * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. * */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Clocks v11.0 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 processor_version: 13.0.1 board: MIMXRT1064-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" #include "fsl_iomuxc.h" /******************************************************************************* * Definitions ******************************************************************************/ /******************************************************************************* * Variables ******************************************************************************/ /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { BOARD_BootClockRUN(); } /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockRUN called_from_default_init: true outputs: - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'} - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} - {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 10 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 132 MHz, locked: true, accuracy: '0.001'} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} - {id: MQS_MCLK.outFreq, value: 1080/17 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} - {id: SAI1_MCLK3.outFreq, value: 30 MHz} - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI2_MCLK3.outFreq, value: 30 MHz} - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} - {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz} - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} - {id: USDHC1_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: USDHC2_CLK_ROOT.outFreq, value: 105.6 MHz} settings: - {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.ARM_PODF.scale, value: '2', locked: true} - {id: CCM.CSI_PODF.scale, value: '1'} - {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.LCDIF_PODF.scale, value: '4', locked: true} - {id: CCM.LCDIF_PRED.scale, value: '2', locked: true} - {id: CCM.LPI2C_CLK_PODF.scale, value: '6', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '4', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '8'} - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK} - {id: CCM.TRACE_PODF.scale, value: '4', locked: true} - {id: CCM.USDHC1_PODF.scale, value: '5'} - {id: CCM.USDHC2_PODF.scale, value: '5'} - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} - {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18'} - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} - {id: CCM_ANALOG.PLL3_PFD1_DIV.scale, value: '16', locked: true} - {id: CCM_ANALOG.PLL3_PFD1_MUL.scale, value: '18', locked: true} - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} - {id: CCM_ANALOG.PLL4.denom, value: '50'} - {id: CCM_ANALOG.PLL4.div, value: '47'} - {id: CCM_ANALOG.PLL5.denom, value: '1'} - {id: CCM_ANALOG.PLL5.div, value: '31', locked: true} - {id: CCM_ANALOG.PLL5.num, value: '0'} - {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV} - {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true} - {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true} - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} - {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'} sources: - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockRUN configuration ******************************************************************************/ const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ .numerator = 0, /* 30 bit numerator of fractional loop divider */ .denominator = 1, /* 30 bit denominator of fractional loop divider */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = { .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ .postDivider = 8, /* Divider after PLL */ .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ }; /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ void BOARD_BootClockRUN(void) { /* Init RTC OSC clock frequency. */ CLOCK_SetRtcXtalFreq(32768U); /* Enable 1MHz clock output. */ XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; /* Use free 1MHz clock output. */ XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; /* Set XTAL 24MHz clock frequency. */ CLOCK_SetXtalFreq(24000000U); /* Enable XTAL 24MHz clock source. */ CLOCK_InitExternalClk(0); /* Enable internal RC. */ CLOCK_InitRcOsc24M(); /* Switch clock source to external OSC. */ CLOCK_SwitchOsc(kCLOCK_XtalOsc); /* Set Oscillator ready counter value. */ CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); /* Waiting for DCDC_STS_DC_OK bit is asserted */ while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ CLOCK_DisableClock(kCLOCK_Adc1); CLOCK_DisableClock(kCLOCK_Adc2); CLOCK_DisableClock(kCLOCK_Xbar1); CLOCK_DisableClock(kCLOCK_Xbar2); CLOCK_DisableClock(kCLOCK_Xbar3); /* Set IPG_PODF. */ CLOCK_SetDiv(kCLOCK_IpgDiv, 3); /* Set ARM_PODF. */ CLOCK_SetDiv(kCLOCK_ArmDiv, 1); /* Set PERIPH_CLK2_PODF. */ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); /* Disable PERCLK clock gate. */ CLOCK_DisableClock(kCLOCK_Gpt1); CLOCK_DisableClock(kCLOCK_Gpt1S); CLOCK_DisableClock(kCLOCK_Gpt2); CLOCK_DisableClock(kCLOCK_Gpt2S); CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ CLOCK_SetDiv(kCLOCK_Usdhc1Div, 4); /* Set Usdhc1 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); /* Disable USDHC2 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc2); /* Set USDHC2_PODF. */ CLOCK_SetDiv(kCLOCK_Usdhc2Div, 4); /* Set Usdhc2 clock source. */ CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT /* Disable Semc clock gate. */ CLOCK_DisableClock(kCLOCK_Semc); /* Set SEMC_PODF. */ CLOCK_SetDiv(kCLOCK_SemcDiv, 7); /* Set Semc alt clock source. */ CLOCK_SetMux(kCLOCK_SemcAltMux, 0); /* Set Semc clock source. */ CLOCK_SetMux(kCLOCK_SemcMux, 0); #endif /* Disable Flexspi clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi); /* Set FLEXSPI_PODF. */ CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); /* Set Flexspi clock source. */ CLOCK_SetMux(kCLOCK_FlexspiMux, 3); /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Disable Flexspi2 clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi2); /* Set FLEXSPI2_PODF. */ CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); /* Set Flexspi2 clock source. */ CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); #endif /* Disable CSI clock gate. */ CLOCK_DisableClock(kCLOCK_Csi); /* Set CSI_PODF. */ CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set Csi clock source. */ CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Disable LPSPI clock gate. */ CLOCK_DisableClock(kCLOCK_Lpspi1); CLOCK_DisableClock(kCLOCK_Lpspi2); CLOCK_DisableClock(kCLOCK_Lpspi3); CLOCK_DisableClock(kCLOCK_Lpspi4); /* Set LPSPI_PODF. */ CLOCK_SetDiv(kCLOCK_LpspiDiv, 3); /* Set Lpspi clock source. */ CLOCK_SetMux(kCLOCK_LpspiMux, 2); /* Disable TRACE clock gate. */ CLOCK_DisableClock(kCLOCK_Trace); /* Set TRACE_PODF. */ CLOCK_SetDiv(kCLOCK_TraceDiv, 3); /* Set Trace clock source. */ CLOCK_SetMux(kCLOCK_TraceMux, 0); /* Disable SAI1 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai1); /* Set SAI1_CLK_PRED. */ CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); /* Set SAI1_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Sai1Div, 1); /* Set Sai1 clock source. */ CLOCK_SetMux(kCLOCK_Sai1Mux, 0); /* Disable SAI2 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai2); /* Set SAI2_CLK_PRED. */ CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); /* Set SAI2_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Sai2Div, 1); /* Set Sai2 clock source. */ CLOCK_SetMux(kCLOCK_Sai2Mux, 0); /* Disable SAI3 clock gate. */ CLOCK_DisableClock(kCLOCK_Sai3); /* Set SAI3_CLK_PRED. */ CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); /* Set SAI3_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Sai3Div, 1); /* Set Sai3 clock source. */ CLOCK_SetMux(kCLOCK_Sai3Mux, 0); /* Disable Lpi2c clock gate. */ CLOCK_DisableClock(kCLOCK_Lpi2c1); CLOCK_DisableClock(kCLOCK_Lpi2c2); CLOCK_DisableClock(kCLOCK_Lpi2c3); /* Set LPI2C_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set Lpi2c clock source. */ CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Disable CAN clock gate. */ CLOCK_DisableClock(kCLOCK_Can1); CLOCK_DisableClock(kCLOCK_Can2); CLOCK_DisableClock(kCLOCK_Can3); CLOCK_DisableClock(kCLOCK_Can1S); CLOCK_DisableClock(kCLOCK_Can2S); CLOCK_DisableClock(kCLOCK_Can3S); /* Set CAN_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_CanDiv, 1); /* Set Can clock source. */ CLOCK_SetMux(kCLOCK_CanMux, 2); /* Disable UART clock gate. */ CLOCK_DisableClock(kCLOCK_Lpuart1); CLOCK_DisableClock(kCLOCK_Lpuart2); CLOCK_DisableClock(kCLOCK_Lpuart3); CLOCK_DisableClock(kCLOCK_Lpuart4); CLOCK_DisableClock(kCLOCK_Lpuart5); CLOCK_DisableClock(kCLOCK_Lpuart6); CLOCK_DisableClock(kCLOCK_Lpuart7); CLOCK_DisableClock(kCLOCK_Lpuart8); /* Set UART_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set Uart clock source. */ CLOCK_SetMux(kCLOCK_UartMux, 0); /* Disable LCDIF clock gate. */ CLOCK_DisableClock(kCLOCK_LcdPixel); /* Set LCDIF_PRED. */ CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); /* Set LCDIF_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); /* Set Lcdif pre clock source. */ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); /* Disable SPDIF clock gate. */ CLOCK_DisableClock(kCLOCK_Spdif); /* Set SPDIF0_CLK_PRED. */ CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); /* Set SPDIF0_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); /* Set Spdif clock source. */ CLOCK_SetMux(kCLOCK_SpdifMux, 3); /* Disable Flexio1 clock gate. */ CLOCK_DisableClock(kCLOCK_Flexio1); /* Set FLEXIO1_CLK_PRED. */ CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); /* Set FLEXIO1_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); /* Set Flexio1 clock source. */ CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); /* Disable Flexio2 clock gate. */ CLOCK_DisableClock(kCLOCK_Flexio2); /* Set FLEXIO2_CLK_PRED. */ CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); /* Set FLEXIO2_CLK_PODF. */ CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); /* Set Flexio2 clock source. */ CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); /* Set Pll3 sw clock source. */ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); /* Init ARM PLL. */ CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ #ifndef SKIP_SYSCLK_INIT #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." #endif /* Init System PLL. */ CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); /* Init System pfd0. */ CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); /* Init System pfd1. */ CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); /* Init System pfd2. */ CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); /* Init System pfd3. */ CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); #endif /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) /* Init Usb1 PLL. */ CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); /* Init Usb1 pfd0. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); /* Init Usb1 pfd1. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); /* Init Usb1 pfd2. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); /* Init Usb1 pfd3. */ CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); /* Disable Usb1 PLL output for USBPHY1. */ CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; #endif /* DeInit Audio PLL. */ CLOCK_DeinitAudioPll(); /* Bypass Audio PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); /* Set divider for Audio PLL. */ CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; /* Enable Audio PLL output. */ CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; /* Init Video PLL. */ uint32_t pllVideo; /* Disable Video PLL output before initial Video PLL. */ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; /* Bypass PLL first */ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0); CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0); CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1); pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31); pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3); CCM_ANALOG->PLL_VIDEO = pllVideo; while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) { } /* Disable bypass for Video PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0); /* DeInit Enet PLL. */ CLOCK_DeinitEnetPll(); /* Bypass Enet PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); /* Set Enet output divider. */ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); /* Enable Enet output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; /* Set Enet2 output divider. */ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); /* Enable Enet2 output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; /* Enable Enet25M output. */ CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; /* DeInit Usb2 PLL. */ CLOCK_DeinitUsb2Pll(); /* Bypass Usb2 PLL. */ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); /* Enable Usb2 PLL output. */ CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; /* Set preperiph clock source. */ CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* Set periph clock source. */ CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set periph clock2 clock source. */ CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); /* Set per clock source. */ CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Set lvds1 clock source. */ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); /* Set clock out1 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); /* Set clock out1 source. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); /* Set clock out2 divider. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); /* Set clock out2 source. */ CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); /* Set clock out1 drives clock out1. */ CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; /* Disable clock out1. */ CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; /* Disable clock out2. */ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; /* Set SAI1 MCLK1 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); /* Set SAI1 MCLK2 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); /* Set SAI1 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); /* Set SAI2 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); /* Set SAI3 MCLK3 clock source. */ IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); /* Set MQS configuration. */ IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); /* Set ENET Ref clock source. */ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; /* Set ENET2 Ref clock source. */ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; /* Set GPT1 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; /* Set GPT2 High frequency reference clock source. */ IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; }