From 884ccfb04867bf82961359ae95fd3803b03ddfa2 Mon Sep 17 00:00:00 2001
From: Michele Balistreri <michele@bitgamma.com>
Date: Wed, 8 Mar 2023 10:05:30 +0100
Subject: [PATCH] use TRNG for nxp port

---
 nxp/.cproject                                 |   59 +-
 .../lists/fsl_component_generic_list.c        |  493 ------
 .../lists/fsl_component_generic_list.h        |  219 ---
 nxp/component/rng/fsl_adapter_rng.h           |  102 --
 nxp/component/rng/fsl_adapter_trng.c          |   76 -
 nxp/drivers/fsl_cache.c                       |  602 +++++++
 nxp/drivers/fsl_cache.h                       |  457 ++++++
 nxp/drivers/fsl_dcp.c                         | 1461 +++++++++++++++++
 nxp/drivers/fsl_dcp.h                         |  580 +++++++
 nxp/source/nxp.c                              |    9 +
 10 files changed, 3121 insertions(+), 937 deletions(-)
 delete mode 100644 nxp/component/lists/fsl_component_generic_list.c
 delete mode 100644 nxp/component/lists/fsl_component_generic_list.h
 delete mode 100644 nxp/component/rng/fsl_adapter_rng.h
 delete mode 100644 nxp/component/rng/fsl_adapter_trng.c
 create mode 100644 nxp/drivers/fsl_cache.c
 create mode 100644 nxp/drivers/fsl_cache.h
 create mode 100644 nxp/drivers/fsl_dcp.c
 create mode 100644 nxp/drivers/fsl_dcp.h

diff --git a/nxp/.cproject b/nxp/.cproject
index 37b990f..578f04c 100644
--- a/nxp/.cproject
+++ b/nxp/.cproject
@@ -127,26 +127,9 @@
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/serial_manager}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/uart}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/utilities}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/video}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/rng}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/lists}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/app}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/portable/GCC/ARM_CM4F}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/drivers}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/xip}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/device}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/CMSIS}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/serial_manager}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/uart}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/utilities}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/video}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/rng}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/lists}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
 								</option>
 								<option id="gnu.c.compiler.option.include.files.1173281163" name="Include files (-include)" superClass="gnu.c.compiler.option.include.files" useByScannerDiscovery="false"/>
 								<option id="com.crt.advproject.gcc.exe.debug.option.optimization.level.448438111" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.debug.option.optimization.level" useByScannerDiscovery="true"/>
@@ -207,8 +190,6 @@
 								<option id="com.crt.advproject.gas.arch.1100564935" name="Architecture" superClass="com.crt.advproject.gas.arch" useByScannerDiscovery="false" value="com.crt.advproject.gas.target.cm7" valueType="enumerated"/>
 								<option id="gnu.both.asm.option.flags.crt.117618328" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" useByScannerDiscovery="false" value="-c -x assembler-with-cpp -D__REDLIB__" valueType="string"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.both.asm.option.include.paths.176080348" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/portable/GCC/ARM_CM4F}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/drivers}&quot;"/>
@@ -218,9 +199,9 @@
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/serial_manager}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/uart}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/utilities}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/video}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/rng}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/lists}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/app}&quot;"/>
 								</option>
 								<option id="gnu.both.asm.option.warnings.nowarn.801402127" name="Suppress warnings (-W)" superClass="gnu.both.asm.option.warnings.nowarn" useByScannerDiscovery="false"/>
 								<option id="gnu.both.asm.option.version.227740303" name="Announce version (-v)" superClass="gnu.both.asm.option.version" useByScannerDiscovery="false"/>
@@ -396,11 +377,11 @@
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="component"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
-						<entry excluding="freertos_kernel/portable/MemMang/heap_1.c|freertos_kernel/portable/MemMang/heap_2.c|freertos_kernel/portable/MemMang/heap_3.c|freertos_kernel/portable/MemMang/heap_5.c|freertos_kernel/portable/MemMang/heap_4.c" flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="xip"/>
+						<entry excluding="freertos_kernel/portable/MemMang/heap_1.c|freertos_kernel/portable/MemMang/heap_2.c|freertos_kernel/portable/MemMang/heap_3.c|freertos_kernel/portable/MemMang/heap_5.c|freertos_kernel/portable/MemMang/heap_4.c" flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -528,25 +509,9 @@
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/serial_manager}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/uart}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/utilities}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/video}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/rng}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/lists}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/include}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/portable/GCC/ARM_CM4F}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/drivers}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/xip}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/device}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/CMSIS}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/serial_manager}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/uart}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/utilities}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/video}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/rng}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/lists}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/app}&quot;"/>
 								</option>
 								<option id="gnu.c.compiler.option.include.files.271263686" name="Include files (-include)" superClass="gnu.c.compiler.option.include.files" useByScannerDiscovery="false"/>
 								<option id="gnu.c.compiler.option.optimization.flags.781262918" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" useByScannerDiscovery="false" value="-fno-common" valueType="string"/>
@@ -605,8 +570,6 @@
 								<option id="com.crt.advproject.gas.arch.399457757" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm7" valueType="enumerated"/>
 								<option id="gnu.both.asm.option.flags.crt.1173954126" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__" valueType="string"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.both.asm.option.include.paths.1417120670" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/freertos/freertos_kernel/portable/GCC/ARM_CM4F}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/drivers}&quot;"/>
@@ -616,9 +579,9 @@
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/serial_manager}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/uart}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/utilities}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/video}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/rng}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/component/lists}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/board}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/source}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/app}&quot;"/>
 								</option>
 								<option id="gnu.both.asm.option.warnings.nowarn.708206456" name="Suppress warnings (-W)" superClass="gnu.both.asm.option.warnings.nowarn"/>
 								<option id="gnu.both.asm.option.version.1433379675" name="Announce version (-v)" superClass="gnu.both.asm.option.version"/>
@@ -753,15 +716,17 @@
 					</folderInfo>
 					<sourceEntries>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="CMSIS"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="app"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="board"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="component"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="device"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="drivers"/>
-						<entry excluding="freertos_kernel/portable/MemMang/heap_1.c|freertos_kernel/portable/MemMang/heap_2.c|freertos_kernel/portable/MemMang/heap_3.c|freertos_kernel/portable/MemMang/heap_5.c" flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="source"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="utilities"/>
 						<entry flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="xip"/>
+						<entry excluding="freertos_kernel/portable/MemMang/heap_1.c|freertos_kernel/portable/MemMang/heap_2.c|freertos_kernel/portable/MemMang/heap_3.c|freertos_kernel/portable/MemMang/heap_5.c|freertos_kernel/portable/MemMang/heap_4.c" flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
+						<entry excluding="freertos_kernel/portable/MemMang/heap_1.c|freertos_kernel/portable/MemMang/heap_2.c|freertos_kernel/portable/MemMang/heap_3.c|freertos_kernel/portable/MemMang/heap_5.c" flags="LOCAL|VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="freertos"/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
@@ -790,7 +755,7 @@
 	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
 		<sdkName>SDK_2.x_EVK-MIMXRT1064</sdkName>
 		<sdkVersion>2.12.1</sdkVersion>
-		<sdkComponents>middleware.freertos-kernel.MIMXRT1064;platform.drivers.clock.MIMXRT1064;platform.drivers.xip_device.MIMXRT1064;platform.drivers.nic301.MIMXRT1064;platform.drivers.igpio.MIMXRT1064;platform.drivers.common.MIMXRT1064;platform.drivers.lpuart.MIMXRT1064;platform.drivers.iomuxc.MIMXRT1064;platform.drivers.lpi2c.MIMXRT1064;platform.drivers.trng.MIMXRT1064;platform.drivers.csi.MIMXRT1064;device.MIMXRT1064_CMSIS.MIMXRT1064;device.MIMXRT1064_system.MIMXRT1064;CMSIS_Include_core_cm.MIMXRT1064;platform.utilities.assert.MIMXRT1064;component.serial_manager_uart.MIMXRT1064;component.lpuart_adapter.MIMXRT1064;component.serial_manager.MIMXRT1064;utility.debug_console.MIMXRT1064;platform.drivers.xip_board.evkmimxrt1064.MIMXRT1064;driver.camera-common.MIMXRT1064;driver.camera-device-common.MIMXRT1064;driver.camera-receiver-common.MIMXRT1064;driver.camera-receiver-csi.MIMXRT1064;driver.video-i2c.MIMXRT1064;component.trng_adapter.MIMXRT1064;component.lists.MIMXRT1064;driver.video-common.MIMXRT1064;driver.camera-device-sccb.MIMXRT1064;project_template.evkmimxrt1064.MIMXRT1064;device.MIMXRT1064_startup.MIMXRT1064;middleware.freertos-kernel.extension.MIMXRT1064;middleware.freertos-kernel.template.MIMXRT1064;driver.camera-device-mt9m114.MIMXRT1064;</sdkComponents>
+		<sdkComponents>middleware.freertos-kernel.MIMXRT1064;platform.drivers.clock.MIMXRT1064;platform.drivers.xip_device.MIMXRT1064;platform.drivers.igpio.MIMXRT1064;platform.drivers.common.MIMXRT1064;platform.drivers.lpuart.MIMXRT1064;platform.drivers.iomuxc.MIMXRT1064;platform.drivers.lpi2c.MIMXRT1064;platform.drivers.trng.MIMXRT1064;platform.drivers.csi.MIMXRT1064;device.MIMXRT1064_CMSIS.MIMXRT1064;device.MIMXRT1064_system.MIMXRT1064;CMSIS_Include_core_cm.MIMXRT1064;platform.utilities.assert.MIMXRT1064;component.serial_manager_uart.MIMXRT1064;component.lpuart_adapter.MIMXRT1064;component.serial_manager.MIMXRT1064;utility.debug_console.MIMXRT1064;platform.drivers.xip_board.evkmimxrt1064.MIMXRT1064;project_template.evkmimxrt1064.MIMXRT1064;device.MIMXRT1064_startup.MIMXRT1064;middleware.freertos-kernel.extension.MIMXRT1064;middleware.freertos-kernel.template.MIMXRT1064;platform.drivers.dcp.MIMXRT1064;platform.drivers.cache_armv7_m7.MIMXRT1064;</sdkComponents>
 		<boardId>evkmimxrt1064</boardId>
 		<package>MIMXRT1064DVL6A</package>
 		<core>cm7</core>
diff --git a/nxp/component/lists/fsl_component_generic_list.c b/nxp/component/lists/fsl_component_generic_list.c
deleted file mode 100644
index f33f03c..0000000
--- a/nxp/component/lists/fsl_component_generic_list.c
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- * Copyright 2018-2019, 2022 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*! *********************************************************************************
-*************************************************************************************
-* Include
-*************************************************************************************
-********************************************************************************** */
-#include "fsl_component_generic_list.h"
-
-#if defined(OSA_USED)
-#include "fsl_os_abstraction.h"
-#if (defined(USE_RTOS) && (USE_RTOS > 0U))
-#define LIST_ENTER_CRITICAL() \
-    OSA_SR_ALLOC();           \
-    OSA_ENTER_CRITICAL()
-#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL()
-#else
-#define LIST_ENTER_CRITICAL()
-#define LIST_EXIT_CRITICAL()
-#endif
-#else
-#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ();
-#define LIST_EXIT_CRITICAL()  EnableGlobalIRQ(regPrimask);
-#endif
-
-static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement)
-{
-    list_status_t listStatus = kLIST_Ok;
-#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
-    list_element_handle_t element = list->head;
-#endif
-    if ((list->max != 0U) && (list->max == list->size))
-    {
-        listStatus = kLIST_Full; /*List is full*/
-    }
-#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U))
-    else
-    {
-        while (element != NULL) /*Scan list*/
-        {
-            /* Determine if element is duplicated */
-            if (element == newElement)
-            {
-                listStatus = kLIST_DuplicateError;
-                break;
-            }
-            element = element->next;
-        }
-    }
-#endif
-    return listStatus;
-}
-
-/*! *********************************************************************************
-*************************************************************************************
-* Public functions
-*************************************************************************************
-********************************************************************************** */
-/*! *********************************************************************************
- * \brief     Initializes the list descriptor.
- *
- * \param[in] list - LIST_ handle to init.
- *            max - Maximum number of elements in list. 0 for unlimited.
- *
- * \return void.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-void LIST_Init(list_handle_t list, uint32_t max)
-{
-    list->head = NULL;
-    list->tail = NULL;
-    list->max  = max;
-    list->size = 0;
-}
-
-/*! *********************************************************************************
- * \brief     Gets the list that contains the given element.
- *
- * \param[in] element - Handle of the element.
- *
- * \return NULL if element is orphan.
- *         Handle of the list the element is inserted into.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_handle_t LIST_GetList(list_element_handle_t element)
-{
-    return element->list;
-}
-
-/*! *********************************************************************************
- * \brief     Links element to the tail of the list.
- *
- * \param[in] list - ID of list to insert into.
- *            element - element to add
- *
- * \return kLIST_Full if list is full.
- *         kLIST_Ok if insertion was successful.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)
-{
-    LIST_ENTER_CRITICAL();
-    list_status_t listStatus = kLIST_Ok;
-
-    listStatus = LIST_Error_Check(list, element);
-    if (listStatus == kLIST_Ok) /* Avoiding list status error */
-    {
-        if (list->size == 0U)
-        {
-            list->head = element;
-        }
-        else
-        {
-            list->tail->next = element;
-        }
-#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
-#else
-        element->prev = list->tail;
-#endif
-        element->list = list;
-        element->next = NULL;
-        list->tail    = element;
-        list->size++;
-    }
-
-    LIST_EXIT_CRITICAL();
-    return listStatus;
-}
-
-/*! *********************************************************************************
- * \brief     Links element to the head of the list.
- *
- * \param[in] list - ID of list to insert into.
- *            element - element to add
- *
- * \return kLIST_Full if list is full.
- *         kLIST_Ok if insertion was successful.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)
-{
-    LIST_ENTER_CRITICAL();
-    list_status_t listStatus = kLIST_Ok;
-
-    listStatus = LIST_Error_Check(list, element);
-    if (listStatus == kLIST_Ok) /* Avoiding list status error */
-    {
-        /* Links element to the head of the list */
-        if (list->size == 0U)
-        {
-            list->tail = element;
-        }
-#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
-#else
-        else
-        {
-            list->head->prev = element;
-        }
-        element->prev = NULL;
-#endif
-        element->list = list;
-        element->next = list->head;
-        list->head    = element;
-        list->size++;
-    }
-
-    LIST_EXIT_CRITICAL();
-    return listStatus;
-}
-
-/*! *********************************************************************************
- * \brief     Unlinks element from the head of the list.
- *
- * \param[in] list - ID of list to remove from.
- *
- * \return NULL if list is empty.
- *         ID of removed element(pointer) if removal was successful.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_element_handle_t LIST_RemoveHead(list_handle_t list)
-{
-    list_element_handle_t element;
-
-    LIST_ENTER_CRITICAL();
-
-    if ((NULL == list) || (list->size == 0U))
-    {
-        element = NULL; /*LIST_ is empty*/
-    }
-    else
-    {
-        element = list->head;
-        list->size--;
-        if (list->size == 0U)
-        {
-            list->tail = NULL;
-        }
-#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
-#else
-        else
-        {
-            element->next->prev = NULL;
-        }
-#endif
-        element->list = NULL;
-        list->head    = element->next; /*Is NULL if element is head*/
-    }
-
-    LIST_EXIT_CRITICAL();
-    return element;
-}
-
-/*! *********************************************************************************
- * \brief     Gets head element ID.
- *
- * \param[in] list - ID of list.
- *
- * \return NULL if list is empty.
- *         ID of head element if list is not empty.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_element_handle_t LIST_GetHead(list_handle_t list)
-{
-    return list->head;
-}
-
-/*! *********************************************************************************
- * \brief     Gets next element ID.
- *
- * \param[in] element - ID of the element.
- *
- * \return NULL if element is tail.
- *         ID of next element if exists.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_element_handle_t LIST_GetNext(list_element_handle_t element)
-{
-    return element->next;
-}
-
-/*! *********************************************************************************
- * \brief     Gets previous element ID.
- *
- * \param[in] element - ID of the element.
- *
- * \return NULL if element is head.
- *         ID of previous element if exists.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_element_handle_t LIST_GetPrev(list_element_handle_t element)
-{
-#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
-    return NULL;
-#else
-    return element->prev;
-#endif
-}
-
-/*! *********************************************************************************
- * \brief     Unlinks an element from its list.
- *
- * \param[in] element - ID of the element to remove.
- *
- * \return kLIST_OrphanElement if element is not part of any list.
- *         kLIST_Ok if removal was successful.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_status_t LIST_RemoveElement(list_element_handle_t element)
-{
-    list_status_t listStatus = kLIST_Ok;
-    LIST_ENTER_CRITICAL();
-
-    if (element->list == NULL)
-    {
-        listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
-    }
-    else
-    {
-#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
-        list_element_handle_t element_list = element->list->head;
-        while (NULL != element_list)
-        {
-            if (element->list->head == element)
-            {
-                element->list->head = element_list->next;
-                break;
-            }
-            if (element_list->next == element)
-            {
-                element_list->next = element->next;
-                break;
-            }
-            element_list = element_list->next;
-        }
-#else
-        if (element->prev == NULL) /*Element is head or solo*/
-        {
-            element->list->head = element->next; /*is null if solo*/
-        }
-        if (element->next == NULL) /*Element is tail or solo*/
-        {
-            element->list->tail = element->prev; /*is null if solo*/
-        }
-        if (element->prev != NULL) /*Element is not head*/
-        {
-            element->prev->next = element->next;
-        }
-        if (element->next != NULL) /*Element is not tail*/
-        {
-            element->next->prev = element->prev;
-        }
-#endif
-        element->list->size--;
-        element->list = NULL;
-    }
-
-    LIST_EXIT_CRITICAL();
-    return listStatus;
-}
-
-/*! *********************************************************************************
- * \brief     Links an element in the previous position relative to a given member
- *            of a list.
- *
- * \param[in] element - ID of a member of a list.
- *            newElement - new element to insert before the given member.
- *
- * \return kLIST_OrphanElement if element is not part of any list.
- *         kLIST_Full if list is full.
- *         kLIST_Ok if insertion was successful.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)
-{
-    list_status_t listStatus = kLIST_Ok;
-    LIST_ENTER_CRITICAL();
-
-    if (element->list == NULL)
-    {
-        listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/
-    }
-    else
-    {
-        listStatus = LIST_Error_Check(element->list, newElement);
-        if (listStatus == kLIST_Ok)
-        {
-#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
-            list_element_handle_t element_list = element->list->head;
-            while (NULL != element_list)
-            {
-                if ((element_list->next == element) || (element_list == element))
-                {
-                    if (element_list == element)
-                    {
-                        element->list->head = newElement;
-                    }
-                    else
-                    {
-                        element_list->next = newElement;
-                    }
-                    newElement->list = element->list;
-                    newElement->next = element;
-                    element->list->size++;
-                    break;
-                }
-                element_list = element_list->next;
-            }
-
-#else
-            if (element->prev == NULL) /*Element is list head*/
-            {
-                element->list->head = newElement;
-            }
-            else
-            {
-                element->prev->next = newElement;
-            }
-            newElement->list = element->list;
-            element->list->size++;
-            newElement->next = element;
-            newElement->prev = element->prev;
-            element->prev = newElement;
-#endif
-        }
-    }
-
-    LIST_EXIT_CRITICAL();
-    return listStatus;
-}
-
-/*! *********************************************************************************
- * \brief     Gets the current size of a list.
- *
- * \param[in] list - ID of the list.
- *
- * \return Current size of the list.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-uint32_t LIST_GetSize(list_handle_t list)
-{
-    return list->size;
-}
-
-/*! *********************************************************************************
- * \brief     Gets the number of free places in the list.
- *
- * \param[in] list - ID of the list.
- *
- * \return Available size of the list.
- *
- * \pre
- *
- * \post
- *
- * \remarks
- *
- ********************************************************************************** */
-uint32_t LIST_GetAvailableSize(list_handle_t list)
-{
-    return (list->max - list->size); /*Gets the number of free places in the list*/
-}
diff --git a/nxp/component/lists/fsl_component_generic_list.h b/nxp/component/lists/fsl_component_generic_list.h
deleted file mode 100644
index aa468e2..0000000
--- a/nxp/component/lists/fsl_component_generic_list.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright 2018-2020, 2022 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _GENERIC_LIST_H_
-#define _GENERIC_LIST_H_
-
-#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON
-#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U)
-#endif
-#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
-#include "fsl_common.h"
-#else
-#endif
-/*!
- * @addtogroup GenericList
- * @{
- */
-
-/**********************************************************************************
- * Include
- ***********************************************************************************/
-
-/**********************************************************************************
- * Public macro definitions
- ***********************************************************************************/
-/*! @brief Definition to determine whether use list light. */
-#ifndef GENERIC_LIST_LIGHT
-#define GENERIC_LIST_LIGHT (1)
-#endif
-
-/*! @brief Definition to determine whether enable list duplicated checking. */
-#ifndef GENERIC_LIST_DUPLICATED_CHECKING
-#define GENERIC_LIST_DUPLICATED_CHECKING (0)
-#endif
-
-/**********************************************************************************
- * Public type definitions
- ***********************************************************************************/
-/*! @brief The list status */
-#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U))
-typedef enum _list_status
-{
-    kLIST_Ok             = kStatus_Success,                   /*!< Success */
-    kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
-    kLIST_Full           = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
-    kLIST_Empty          = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
-    kLIST_OrphanElement  = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
-    kLIST_NotSupport     = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support  */
-} list_status_t;
-#else
-typedef enum _list_status
-{
-    kLIST_Ok             = 0, /*!< Success */
-    kLIST_DuplicateError = 1, /*!< Duplicate Error */
-    kLIST_Full           = 2, /*!< FULL */
-    kLIST_Empty          = 3, /*!< Empty */
-    kLIST_OrphanElement  = 4, /*!< Orphan Element */
-    kLIST_NotSupport     = 5, /*!< Not Support  */
-} list_status_t;
-#endif
-
-/*! @brief The list structure*/
-typedef struct list_label
-{
-    struct list_element_tag *head; /*!< list head */
-    struct list_element_tag *tail; /*!< list tail */
-    uint32_t size;                 /*!< list size */
-    uint32_t max;                  /*!< list max number of elements */
-} list_label_t, *list_handle_t;
-#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U))
-/*! @brief The list element*/
-typedef struct list_element_tag
-{
-    struct list_element_tag *next; /*!< next list element   */
-    struct list_label *list;       /*!< pointer to the list */
-} list_element_t, *list_element_handle_t;
-#else
-/*! @brief The list element*/
-typedef struct list_element_tag
-{
-    struct list_element_tag *next; /*!< next list element   */
-    struct list_element_tag *prev; /*!< previous list element */
-    struct list_label *list;       /*!< pointer to the list */
-} list_element_t, *list_element_handle_t;
-#endif
-/**********************************************************************************
- * Public prototypes
- ***********************************************************************************/
-/**********************************************************************************
- * API
- **********************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-/*!
- * @brief Initialize the list.
- *
- * This function initialize the list.
- *
- * @param list - List handle to initialize.
- * @param max - Maximum number of elements in list. 0 for unlimited.
- */
-void LIST_Init(list_handle_t list, uint32_t max);
-
-/*!
- * @brief Gets the list that contains the given element.
- *
- *
- * @param element - Handle of the element.
- * @retval NULL if element is orphan, Handle of the list the element is inserted into.
- */
-list_handle_t LIST_GetList(list_element_handle_t element);
-
-/*!
- * @brief Links element to the head of the list.
- *
- * @param list - Handle of the list.
- * @param element - Handle of the element.
- * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
- */
-list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);
-
-/*!
- * @brief Links element to the tail of the list.
- *
- * @param list - Handle of the list.
- * @param element - Handle of the element.
- * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
- */
-list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);
-
-/*!
- * @brief Unlinks element from the head of the list.
- *
- * @param list - Handle of the list.
- *
- * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
- */
-list_element_handle_t LIST_RemoveHead(list_handle_t list);
-
-/*!
- * @brief Gets head element handle.
- *
- * @param list - Handle of the list.
- *
- * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
- */
-list_element_handle_t LIST_GetHead(list_handle_t list);
-
-/*!
- * @brief Gets next element handle for given element handle.
- *
- * @param element - Handle of the element.
- *
- * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
- */
-list_element_handle_t LIST_GetNext(list_element_handle_t element);
-
-/*!
- * @brief Gets previous element handle for given element handle.
- *
- * @param element - Handle of the element.
- *
- * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
- */
-list_element_handle_t LIST_GetPrev(list_element_handle_t element);
-
-/*!
- * @brief Unlinks an element from its list.
- *
- * @param element - Handle of the element.
- *
- * @retval kLIST_OrphanElement if element is not part of any list.
- * @retval kLIST_Ok if removal was successful.
- */
-list_status_t LIST_RemoveElement(list_element_handle_t element);
-
-/*!
- * @brief Links an element in the previous position relative to a given member of a list.
- *
- * @param element - Handle of the element.
- * @param newElement - New element to insert before the given member.
- *
- * @retval kLIST_OrphanElement if element is not part of any list.
- * @retval kLIST_Ok if removal was successful.
- */
-list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);
-
-/*!
- * @brief Gets the current size of a list.
- *
- * @param list - Handle of the list.
- *
- * @retval Current size of the list.
- */
-uint32_t LIST_GetSize(list_handle_t list);
-
-/*!
- * @brief Gets the number of free places in the list.
- *
- * @param list - Handle of the list.
- *
- * @retval Available size of the list.
- */
-uint32_t LIST_GetAvailableSize(list_handle_t list);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-/*! @}*/
-#endif /*_GENERIC_LIST_H_*/
diff --git a/nxp/component/rng/fsl_adapter_rng.h b/nxp/component/rng/fsl_adapter_rng.h
deleted file mode 100644
index 667007f..0000000
--- a/nxp/component/rng/fsl_adapter_rng.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _HAL_RNG_H_
-#define _HAL_RNG_H_
-
-#include "fsl_common.h"
-/*!
- * @addtogroup RNG_Adapter
- * @{
- */
-
-/************************************************************************************
-*************************************************************************************
-* Include
-*************************************************************************************
-***********************************************************************************/
-
-/************************************************************************************
-*************************************************************************************
-* Public types
-*************************************************************************************
-************************************************************************************/
-
-/*! @brief Hal rand status. */
-typedef enum _hal_rng_status
-{
-    kStatus_HAL_RngSuccess        = kStatus_Success,                      /*!< Success */
-    KStatus_HAL_RngNotSupport     = MAKE_STATUS(kStatusGroup_HAL_RNG, 1), /*!<Not support*/
-    kStatus_HAL_RngInternalError  = MAKE_STATUS(kStatusGroup_HAL_RNG, 2), /*!<Internal Error*/
-    kStatus_HAL_RngNullPointer    = MAKE_STATUS(kStatusGroup_HAL_RNG, 3), /*!<Null pointer*/
-    kStatus_HAL_RngMaxRequests    = MAKE_STATUS(kStatusGroup_HAL_RNG, 4), /*!<Max request*/
-    kStatus_HAL_RngInvalidArgumen = MAKE_STATUS(kStatusGroup_HAL_RNG, 5), /*!<Invalid Argumen*/
-} hal_rng_status_t;
-/************************************************************************************
-*************************************************************************************
-* Public prototypes
-*************************************************************************************
-************************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @brief Initializes the random adapter module for a random data generator basic operation.
- *
- * @note This API should be called at the beginning of the application using the random adapter driver.
- *
- * @retval kStatus_HAL_RngSuccess Rand module initialize succeed
- */
-hal_rng_status_t HAL_RngInit(void);
-
-/*!
- * @brief DeInitilizate the random adapter module.
- *
- * @note This API should be called when not using the rand adapter driver anymore.
- *
- */
-void HAL_RngDeinit(void);
-
-/*!
- * @brief Get random value from random hardware
- *
- * @note This API should be called to get random data.
- *
- * @param pRandomNo             Pointer to random data
- * @param dataSize            The random data size
- * @retval kStatus_HAL_RngSuccess Rand get data succeed
- */
-hal_rng_status_t HAL_RngHwGetData(void *pRandomNo, uint32_t dataSize);
-
-/*!
- * @brief Get a pseudo random number
- *
- * @note This API should be called to get random data.
- *
- * @param pRandomNo             Pointer to random data
- * @param dataSize            The random data size
- * @retval kStatus_HAL_RngSuccess Rand get data succeed
- */
-hal_rng_status_t HAL_RngGetData(void *pRandomNo, uint32_t dataSize);
-
-/*!
- * @brief Set random seed of random generator hardware
- *
- * @note This API should be called to set seed before get random data.
- *
- * @param seed             Seed of the random hardware generator
- * @retval kStatus_HAL_RngSuccess Rand set rand seed succeed
- * @retval KStatus_HAL_RngNotSupport Rand set rand seed not support
- */
-hal_rng_status_t HAL_RngSetSeed(uint32_t seed);
-#if defined(__cplusplus)
-}
-#endif
-/*! @}*/
-#endif /* _HAL_RNG_H_ */
diff --git a/nxp/component/rng/fsl_adapter_trng.c b/nxp/component/rng/fsl_adapter_trng.c
deleted file mode 100644
index 0b5599e..0000000
--- a/nxp/component/rng/fsl_adapter_trng.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_common.h"
-#include "fsl_adapter_rng.h"
-#include "fsl_trng.h"
-
-hal_rng_status_t HAL_RngInit(void)
-{
-    trng_config_t config;
-    hal_rng_status_t status = kStatus_HAL_RngSuccess;
-    TRNG_Type *trngArr[]    = TRNG_BASE_PTRS;
-    uint32_t randomSeed     = 0;
-
-    (void)TRNG_GetDefaultConfig(&config);
-    config.sampleMode = kTRNG_SampleModeVonNeumann;
-    /* Init TRNG */
-    if ((int32_t)kStatus_InvalidArgument == TRNG_Init(trngArr[0], (void *)&config))
-    {
-        return kStatus_HAL_RngInvalidArgumen;
-    }
-
-    status = HAL_RngHwGetData(&randomSeed, sizeof(randomSeed));
-    if (kStatus_HAL_RngSuccess != status)
-    {
-        return status;
-    }
-    srand(randomSeed);
-    return kStatus_HAL_RngSuccess;
-}
-
-void HAL_RngDeinit(void)
-{
-    TRNG_Type *trngArr[] = TRNG_BASE_PTRS;
-    TRNG_Deinit(trngArr[0]);
-    return;
-}
-
-hal_rng_status_t HAL_RngHwGetData(void *pRandomNo, uint32_t dataSize)
-{
-    TRNG_Type *trngArr[]    = TRNG_BASE_PTRS;
-    hal_rng_status_t status = kStatus_HAL_RngSuccess;
-
-    if (NULL == pRandomNo)
-    {
-        return kStatus_HAL_RngNullPointer;
-    }
-    if ((int32_t)kStatus_Success != TRNG_GetRandomData(trngArr[0], pRandomNo, dataSize))
-    {
-        status = kStatus_HAL_RngInternalError;
-    }
-    return status;
-}
-hal_rng_status_t HAL_RngGetData(void *pRandomNo, uint32_t dataSize)
-{
-    if (NULL == pRandomNo)
-    {
-        return kStatus_HAL_RngNullPointer;
-    }
-
-    for (uint32_t i = 0; i < dataSize; i++)
-    {
-        ((uint8_t *)pRandomNo)[i] = (uint8_t)rand() & 0xFFU;
-    }
-    return kStatus_HAL_RngSuccess;
-}
-
-hal_rng_status_t HAL_RngSetSeed(uint32_t seed)
-{
-    return KStatus_HAL_RngNotSupport;
-}
diff --git a/nxp/drivers/fsl_cache.c b/nxp/drivers/fsl_cache.c
new file mode 100644
index 0000000..721a3fb
--- /dev/null
+++ b/nxp/drivers/fsl_cache.c
@@ -0,0 +1,602 @@
+/*
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cache.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
+#endif
+
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
+#define L2CACHE_8WAYS_MASK        0xFFU
+#define L2CACHE_16WAYS_MASK       0xFFFFU
+#define L2CACHE_SMALLWAYS_NUM     8U
+#define L2CACHE_1KBCOVERTOB       1024U
+#define L2CACHE_SAMLLWAYS_SIZE    16U
+#define L2CACHE_LOCKDOWN_REGNUM   8 /*!< Lock down register numbers.*/
+                                    /*******************************************************************************
+                                     * Prototypes
+                                     ******************************************************************************/
+/*!
+ * @brief Set for all ways and waiting for the operation finished.
+ *  This is provided for all the background operations.
+ *
+ * @param auxCtlReg  The auxiliary control register.
+ * @param regAddr The register address to be operated.
+ */
+static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr);
+
+/*!
+ * @brief Invalidates the Level 2 cache line by physical address.
+ * This function invalidates a cache line by physcial address.
+ *
+ * @param address  The physical addderss of the cache.
+ *        The format of the address shall be :
+ *        bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
+ *              Tag        |    index    |      0
+ *  Note: the physical address shall be aligned to the line size - 32B (256 bit).
+ *  so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
+ *  If the input address is not aligned, it will be changed to 32-byte aligned address.
+ *  The n is varies according to the index width.
+ * @return The actual 32-byte aligned physical address be operated.
+ */
+static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address);
+
+/*!
+ * @brief Cleans the Level 2 cache line based on the physical address.
+ * This function cleans a cache line based on a physcial address.
+ *
+ * @param address  The physical addderss of the cache.
+ *        The format of the address shall be :
+ *        bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
+ *              Tag        |    index    |      0
+ *  Note: the physical address shall be aligned to the line size - 32B (256 bit).
+ *  so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
+ *  If the input address is not aligned, it will be changed to 32-byte aligned address.
+ *  The n is varies according to the index width.
+ * @return The actual 32-byte aligned physical address be operated.
+ */
+static uint32_t L2CACHE_CleanLineByAddr(uint32_t address);
+
+/*!
+ * @brief Cleans and invalidates the Level 2 cache line based on the physical address.
+ * This function cleans and invalidates a cache line based on a physcial address.
+ *
+ * @param address  The physical addderss of the cache.
+ *        The format of the address shall be :
+ *        bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
+ *              Tag        |    index    |      0
+ *  Note: the physical address shall be aligned to the line size - 32B (256 bit).
+ *  so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
+ *  If the input address is not aligned, it will be changed to 32-byte aligned address.
+ *  The n is varies according to the index width.
+ * @return The actual 32-byte aligned physical address be operated.
+ */
+static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address);
+
+/*!
+ * @brief Gets the number of the Level 2 cache and the way size.
+ * This function cleans and invalidates a cache line based on a physcial address.
+ *
+ * @param num_ways  The number of the cache way.
+ * @param size_way  The way size.
+ */
+static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
+{
+    uint16_t mask    = L2CACHE_8WAYS_MASK;
+    uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
+
+    /* Check the ways used at first. */
+    if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
+    {
+        mask = L2CACHE_16WAYS_MASK;
+    }
+
+    /* Set the opeartion for all ways/entries of the cache. */
+    *(uint32_t *)regAddr = mask;
+    /* Waiting for until the operation is complete. */
+    while ((*(volatile uint32_t *)regAddr & mask) && timeout)
+    {
+        __ASM("nop");
+        timeout--;
+    }
+}
+
+static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address)
+{
+    /* Align the address first. */
+    address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
+    /* Invalidate the cache line by physical address. */
+    L2CACHEC->REG7_INV_PA = address;
+
+    return address;
+}
+
+static uint32_t L2CACHE_CleanLineByAddr(uint32_t address)
+{
+    /* Align the address first. */
+    address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
+    /* Invalidate the cache line by physical address. */
+    L2CACHEC->REG7_CLEAN_PA = address;
+
+    return address;
+}
+
+static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address)
+{
+    /* Align the address first. */
+    address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
+    /* Clean and invalidate the cache line by physical address. */
+    L2CACHEC->REG7_CLEAN_INV_PA = address;
+
+    return address;
+}
+
+static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
+{
+    assert(num_ways);
+    assert(size_way);
+
+    uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
+                      L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
+    uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
+                    L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
+
+    *num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM;
+    if (!size)
+    {
+        /* 0 internally mapped to the same size as 1 - 16KB.*/
+        size += 1;
+    }
+    *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
+}
+
+/*!
+ * brief Initializes the level 2 cache controller module.
+ *
+ * param config Pointer to configuration structure. See "l2cache_config_t".
+ */
+void L2CACHE_Init(l2cache_config_t *config)
+{
+    assert(config);
+
+    uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
+    uint8_t count;
+    uint32_t auxReg = 0;
+
+    /*The aux register must be configured when the cachec is disabled
+     * So disable first if the cache controller is enabled.
+     */
+    if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
+    {
+        L2CACHE_Disable();
+    }
+
+    /* Unlock all entries. */
+    if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
+    {
+        waysNum = 0xFFFFU;
+    }
+
+    for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++)
+    {
+        L2CACHE_LockdownByWayEnable(count, waysNum, false);
+    }
+
+    /* Set the ways and way-size etc. */
+    auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
+             L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
+             L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
+             L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
+    L2CACHEC->REG1_AUX_CONTROL = auxReg;
+
+    /* Set the tag/data ram latency. */
+    if (config->lateConfig)
+    {
+        uint32_t data = 0;
+        /* Tag latency. */
+        data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) |
+               L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        L2CACHEC->REG1_TAG_RAM_CONTROL = data;
+        /* Data latency. */
+        data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) |
+               L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
+        L2CACHEC->REG1_DATA_RAM_CONTROL = data;
+    }
+}
+
+/*!
+ * brief Gets an available default settings for the cache controller.
+ *
+ * This function initializes the cache controller configuration structure with default settings.
+ * The default values are:
+ * code
+ *   config->waysNum = kL2CACHE_8ways;
+ *   config->waySize = kL2CACHE_32KbSize;
+ *   config->repacePolicy = kL2CACHE_Roundrobin;
+ *   config->lateConfig = NULL;
+ *   config->istrPrefetchEnable = false;
+ *   config->dataPrefetchEnable = false;
+ *   config->nsLockdownEnable = false;
+ *   config->writeAlloc = kL2CACHE_UseAwcache;
+ * endcode
+ * param config Pointer to the configuration structure.
+ */
+void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
+{
+    assert(config);
+
+    /* Initializes the configure structure to zero. */
+    memset(config, 0, sizeof(*config));
+
+    uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
+                      L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
+    uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
+                    L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
+
+    /* Get the default value */
+    config->wayNum             = (l2cache_way_num_t)number;
+    config->waySize            = (l2cache_way_size)size;
+    config->repacePolicy       = kL2CACHE_Roundrobin;
+    config->lateConfig         = NULL;
+    config->istrPrefetchEnable = false;
+    config->dataPrefetchEnable = false;
+    config->nsLockdownEnable   = false;
+    config->writeAlloc         = kL2CACHE_UseAwcache;
+}
+
+/*!
+ * brief Enables the level 2 cache controller.
+ * This function enables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
+void L2CACHE_Enable(void)
+{
+    /* Invalidate first. */
+    L2CACHE_Invalidate();
+    /* Enable the level 2 cache controller. */
+    L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
+}
+
+/*!
+ * brief Disables the level 2 cache controller.
+ * This function disables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
+void L2CACHE_Disable(void)
+{
+    /* First CleanInvalidate all enties in the cache. */
+    L2CACHE_CleanInvalidate();
+    /* Disable the level 2 cache controller. */
+    L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK;
+    /* DSB - data sync barrier.*/
+    __DSB();
+}
+
+/*!
+ * brief Invalidates the Level 2 cache.
+ * This function invalidates all entries in cache.
+ *
+ */
+void L2CACHE_Invalidate(void)
+{
+    /* Invalidate all entries in cache. */
+    L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY);
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans the level 2 cache controller.
+ * This function cleans all entries in the level 2 cache controller.
+ *
+ */
+void L2CACHE_Clean(void)
+{
+    /* Clean all entries of the cache. */
+    L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY);
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans and invalidates the level 2 cache controller.
+ * This function cleans and invalidates all entries in the level 2 cache controller.
+ *
+ */
+void L2CACHE_CleanInvalidate(void)
+{
+    /* Clean all entries of the cache. */
+    L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY);
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    uint32_t endAddr = address + size_byte;
+
+    /* Invalidate addresses in the range. */
+    while (address < endAddr)
+    {
+        address = L2CACHE_InvalidateLineByAddr(address);
+        /* Update the size. */
+        address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
+    }
+
+    /* Cache sync. */
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
+{
+    uint32_t num_ways = 0;
+    uint32_t size_way = 0;
+    uint32_t endAddr  = address + size_byte;
+
+    /* Get the number and size of the cache way. */
+    L2CACHE_GetWayNumSize(&num_ways, &size_way);
+
+    /* Check if the clean size is over the cache size. */
+    if ((endAddr - address) > num_ways * size_way)
+    {
+        L2CACHE_Clean();
+        return;
+    }
+
+    /* Clean addresses in the range. */
+    while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
+    {
+        /* Clean the address in the range. */
+        address = L2CACHE_CleanLineByAddr(address);
+        address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
+    }
+
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans and invalidates all cache lines between two physical addresses.
+ *
+ * param address  The start address of the memory to be cleaned and invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    uint32_t num_ways = 0;
+    uint32_t size_way = 0;
+    uint32_t endAddr  = address + size_byte;
+
+    /* Get the number and size of the cache way. */
+    L2CACHE_GetWayNumSize(&num_ways, &size_way);
+
+    /* Check if the clean size is over the cache size. */
+    if ((endAddr - address) > num_ways * size_way)
+    {
+        L2CACHE_CleanInvalidate();
+        return;
+    }
+
+    /* Clean addresses in the range. */
+    while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
+    {
+        /* Clean the address in the range. */
+        address = L2CACHE_CleanInvalidateLineByAddr(address);
+        address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
+    }
+
+    L2CACHEC->REG7_CACHE_SYNC = 0;
+}
+
+/*!
+ * brief Enables or disables to lock down the data and instruction by way.
+ * This function locks down the cached instruction/data by way and prevent the adresses from
+ * being allocated and prevent dara from being evicted out of the level 2 cache.
+ * But the normal cache maintenance operations that invalidate, clean or clean
+ * and validate cache contents affect the locked-down cache lines as normal.
+ *
+ * param masterId  The master id, range from 0 ~ 7.
+ * param mask  The ways to be enabled or disabled to lockdown.
+ *               each bit in value is related to each way of the cache. for example:
+ *               value: bit 0  ------ way 0.
+ *               value: bit 1  ------ way 1.
+ *               --------------------------
+ *               value: bit 15 ------ way 15.
+ * Note: please make sure the value setting is align with your supported ways.
+ * param enable  True enable the lockdown, false to disable the lockdown.
+ */
+void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
+{
+    uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
+                       L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
+    num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM;
+
+    assert(mask < (1U << num_ways));
+    assert(masterId < L2CACHE_LOCKDOWN_REGNUM);
+
+    uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN;
+    uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN;
+
+    if (enable)
+    {
+        /* Data lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask;
+        /* Instruction lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask;
+    }
+    else
+    {
+        /* Data lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask;
+        /* Instruction lockdown. */
+        L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
+    }
+}
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+
+/*!
+ * brief Invalidate cortex-m7 L1 instruction cache by range.
+ *
+ * param address  The start address of the memory to be invalidated.
+ * param size_byte  The memory size.
+ * note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 I-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
+{
+#if (__DCACHE_PRESENT == 1U)
+    uint32_t addr      = address & ~((uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1U);
+    uint32_t align_len = address - addr;
+    int32_t size       = (int32_t)size_byte + (int32_t)align_len;
+
+    __DSB();
+    while (size > 0)
+    {
+        SCB->ICIMVAU = addr;
+        addr += (uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
+        size -= (int32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE;
+    }
+    __DSB();
+    __ISB();
+#endif
+}
+
+/*!
+ * brief Invalidates all instruction caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_InvalidateByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+
+    L1CACHE_InvalidateICacheByRange(address, size_byte);
+}
+
+/*!
+ * brief Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_InvalidateByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+    L1CACHE_InvalidateDCacheByRange(address, size_byte);
+}
+
+/*!
+ * brief Cleans all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
+{
+    L1CACHE_CleanDCacheByRange(address, size_byte);
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_CleanByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+}
+
+/*!
+ * brief Cleans and Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * param address The physical address.
+ * param size_byte size of the memory to be cleaned and invalidated.
+ * note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
+{
+    L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
+    L2CACHE_CleanInvalidateByRange(address, size_byte);
+#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+}
diff --git a/nxp/drivers/fsl_cache.h b/nxp/drivers/fsl_cache.h
new file mode 100644
index 0000000..9708edd
--- /dev/null
+++ b/nxp/drivers/fsl_cache.h
@@ -0,0 +1,457 @@
+/*
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_CACHE_H_
+#define _FSL_CACHE_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cache_armv7_m7
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief cache driver version 2.0.4. */
+#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
+#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
+#endif
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+
+/*! @brief Number of level 2 cache controller ways. */
+typedef enum _l2cache_way_num
+{
+    kL2CACHE_8ways = 0, /*!< 8 ways. */
+#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
+    kL2CACHE_16ways /*!< 16 ways. */
+#endif              /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
+} l2cache_way_num_t;
+
+/*! @brief Level 2 cache controller way size. */
+typedef enum _l2cache_way_size
+{
+    kL2CACHE_16KBSize  = 1, /*!< 16 KB way size. */
+    kL2CACHE_32KBSize  = 2, /*!< 32 KB way size. */
+    kL2CACHE_64KBSize  = 3, /*!< 64 KB way size. */
+    kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
+    kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
+    kL2CACHE_512KBSize = 6  /*!< 512 KB way size. */
+} l2cache_way_size;
+
+/*! @brief Level 2 cache controller replacement policy. */
+typedef enum _l2cache_replacement
+{
+    kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
+    kL2CACHE_Roundrobin         /*!< Round-robin replacemnt policy. */
+} l2cache_replacement_t;
+
+/*! @brief Level 2 cache controller force write allocate options. */
+typedef enum _l2cache_writealloc
+{
+    kL2CACHE_UseAwcache = 0,    /*!< Use AWCAHE attribute for the write allocate. */
+    kL2CACHE_NoWriteallocate,   /*!< Force no write allocate. */
+    kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
+} l2cache_writealloc_t;
+
+/*! @brief Level 2 cache controller tag/data ram latency. */
+typedef enum _l2cache_latency
+{
+    kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
+    kL2CACHE_2CycleLate,     /*!< 2 cycle of latency. */
+    kL2CACHE_3CycleLate,     /*!< 3 cycle of latency. */
+    kL2CACHE_4CycleLate,     /*!< 4 cycle of latency. */
+    kL2CACHE_5CycleLate,     /*!< 5 cycle of latency. */
+    kL2CACHE_6CycleLate,     /*!< 6 cycle of latency. */
+    kL2CACHE_7CycleLate,     /*!< 7 cycle of latency. */
+    kL2CACHE_8CycleLate      /*!< 8 cycle of latency. */
+} l2cache_latency_t;
+
+/*! @brief Level 2 cache controller tag/data ram latency configure structure. */
+typedef struct _l2cache_latency_config
+{
+    l2cache_latency_t tagWriteLate;  /*!< Tag write latency. */
+    l2cache_latency_t tagReadLate;   /*!< Tag Read latency. */
+    l2cache_latency_t tagSetupLate;  /*!< Tag setup latency. */
+    l2cache_latency_t dataWriteLate; /*!< Data write latency. */
+    l2cache_latency_t dataReadLate;  /*!< Data Read latency. */
+    l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
+} L2cache_latency_config_t;
+
+/*! @brief Level 2 cache controller configure structure. */
+typedef struct _l2cache_config
+{
+    /* ------------------------ l2 cachec basic settings ---------------------------- */
+    l2cache_way_num_t wayNum;           /*!< The number of ways. */
+    l2cache_way_size waySize;           /*!< The way size = Cache Ram size / wayNum. */
+    l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */
+    /* ------------------------ tag/data ram latency settings ----------------------- */
+    L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
+    /* ------------------------ Prefetch enable settings ---------------------------- */
+    bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
+    bool dataPrefetchEnable; /*!< Data prefetch enable. */
+    /* ------------------------ Non-secure access settings -------------------------- */
+    bool nsLockdownEnable; /*!< None-secure lockdown enable. */
+    /* ------------------------ other settings -------------------------------------- */
+    l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */
+} l2cache_config_t;
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Control for cortex-m7 L1 cache
+ *@{
+ */
+
+/*!
+ * @brief Enables cortex-m7 L1 instruction cache.
+ *
+ */
+static inline void L1CACHE_EnableICache(void)
+{
+    SCB_EnableICache();
+}
+
+/*!
+ * @brief Disables cortex-m7 L1 instruction cache.
+ *
+ */
+static inline void L1CACHE_DisableICache(void)
+{
+    SCB_DisableICache();
+}
+
+/*!
+ * @brief Invalidate cortex-m7 L1 instruction cache.
+ *
+ */
+static inline void L1CACHE_InvalidateICache(void)
+{
+    SCB_InvalidateICache();
+}
+
+/*!
+ * @brief Invalidate cortex-m7 L1 instruction cache by range.
+ *
+ * @param address  The start address of the memory to be invalidated.
+ * @param size_byte  The memory size.
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 I-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Enables cortex-m7 L1 data cache.
+ *
+ */
+static inline void L1CACHE_EnableDCache(void)
+{
+    SCB_EnableDCache();
+}
+
+/*!
+ * @brief Disables cortex-m7 L1 data cache.
+ *
+ */
+static inline void L1CACHE_DisableDCache(void)
+{
+    SCB_DisableDCache();
+}
+
+/*!
+ * @brief Invalidates cortex-m7 L1 data cache.
+ *
+ */
+static inline void L1CACHE_InvalidateDCache(void)
+{
+    SCB_InvalidateDCache();
+}
+
+/*!
+ * @brief Cleans cortex-m7 L1 data cache.
+ *
+ */
+static inline void L1CACHE_CleanDCache(void)
+{
+    SCB_CleanDCache();
+}
+
+/*!
+ * @brief Cleans and Invalidates cortex-m7 L1 data cache.
+ *
+ */
+static inline void L1CACHE_CleanInvalidateDCache(void)
+{
+    SCB_CleanInvalidateDCache();
+}
+
+/*!
+ * @brief Invalidates cortex-m7 L1 data cache by range.
+ *
+ * @param address  The start address of the memory to be invalidated.
+ * @param size_byte  The memory size.
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 D-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
+{
+    SCB_InvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
+}
+
+/*!
+ * @brief Cleans cortex-m7 L1 data cache by range.
+ *
+ * @param address  The start address of the memory to be cleaned.
+ * @param size_byte  The memory size.
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 D-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
+{
+    SCB_CleanDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
+}
+
+/*!
+ * @brief Cleans and Invalidates cortex-m7 L1 data cache by range.
+ *
+ * @param address  The start address of the memory to be clean and invalidated.
+ * @param size_byte  The memory size.
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L1 D-cache line size if
+ * startAddr is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
+{
+    SCB_CleanInvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
+}
+/*@}*/
+
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
+/*!
+ * @name Control for L2 pl310 cache
+ *@{
+ */
+
+/*!
+ * @brief Initializes the level 2 cache controller module.
+ *
+ * @param config Pointer to configuration structure. See "l2cache_config_t".
+ */
+void L2CACHE_Init(l2cache_config_t *config);
+
+/*!
+ * @brief Gets an available default settings for the cache controller.
+ *
+ * This function initializes the cache controller configuration structure with default settings.
+ * The default values are:
+ * @code
+ *   config->waysNum = kL2CACHE_8ways;
+ *   config->waySize = kL2CACHE_32KbSize;
+ *   config->repacePolicy = kL2CACHE_Roundrobin;
+ *   config->lateConfig = NULL;
+ *   config->istrPrefetchEnable = false;
+ *   config->dataPrefetchEnable = false;
+ *   config->nsLockdownEnable = false;
+ *   config->writeAlloc = kL2CACHE_UseAwcache;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
+
+/*!
+ * @brief Enables the level 2 cache controller.
+ * This function enables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
+void L2CACHE_Enable(void);
+
+/*!
+ * @brief Disables the level 2 cache controller.
+ * This function disables the cache controller. Must be written using a secure access.
+ * If write with a Non-secure access will cause a DECERR response.
+ *
+ */
+void L2CACHE_Disable(void);
+
+/*!
+ * @brief Invalidates the Level 2 cache.
+ * This function invalidates all entries in cache.
+ *
+ */
+void L2CACHE_Invalidate(void);
+
+/*!
+ * @brief Invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function invalidates all cache lines between two physical addresses.
+ *
+ * @param address  The start address of the memory to be invalidated.
+ * @param size_byte  The memory size.
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans the level 2 cache controller.
+ * This function cleans all entries in the level 2 cache controller.
+ *
+ */
+void L2CACHE_Clean(void);
+
+/*!
+ * @brief Cleans the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans all cache lines between two physical addresses.
+ *
+ * @param address  The start address of the memory to be cleaned.
+ * @param size_byte  The memory size.
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans and invalidates the level 2 cache controller.
+ * This function cleans and invalidates all entries in the level 2 cache controller.
+ *
+ */
+void L2CACHE_CleanInvalidate(void);
+
+/*!
+ * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
+ * This function cleans and invalidates all cache lines between two physical addresses.
+ *
+ * @param address  The start address of the memory to be cleaned and invalidated.
+ * @param size_byte  The memory size.
+ * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
+ * The startAddr here will be forced to align to L2 line size if startAddr
+ * is not aligned. For the size_byte, application should make sure the
+ * alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Enables or disables to lock down the data and instruction by way.
+ * This function locks down the cached instruction/data by way and prevent the adresses from
+ * being allocated and prevent dara from being evicted out of the level 2 cache.
+ * But the normal cache maintenance operations that invalidate, clean or clean
+ * and validate cache contents affect the locked-down cache lines as normal.
+ *
+ * @param masterId  The master id, range from 0 ~ 7.
+ * @param mask  The ways to be enabled or disabled to lockdown.
+ *               each bit in value is related to each way of the cache. for example:
+ *               value: bit 0  ------ way 0.
+ *               value: bit 1  ------ way 1.
+ *               --------------------------
+ *               value: bit 15 ------ way 15.
+ * Note: please make sure the value setting is align with your supported ways.
+ * @param enable  True enable the lockdown, false to disable the lockdown.
+ */
+void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
+
+/*@}*/
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
+
+/*!
+ * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
+ * Mainly used for many drivers for easy cache operation.
+ *@{
+ */
+
+/*!
+ * @brief Invalidates all instruction caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be invalidated.
+ * @note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be invalidated.
+ * @note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be cleaned.
+ * @note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
+
+/*!
+ * @brief Cleans and Invalidates all data caches by range.
+ *
+ * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
+ *
+ * @param address The physical address.
+ * @param size_byte size of the memory to be cleaned and invalidated.
+ * @note address and size should be aligned to cache line size
+ *  32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
+ * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
+ * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
+ */
+void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CACHE_H_*/
diff --git a/nxp/drivers/fsl_dcp.c b/nxp/drivers/fsl_dcp.c
new file mode 100644
index 0000000..a0b82ba
--- /dev/null
+++ b/nxp/drivers/fsl_dcp.c
@@ -0,0 +1,1461 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dcp.h"
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+#include "fsl_cache.h"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dcp"
+#endif
+
+/*! Compile time sizeof() check */
+#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
+
+#define dcp_memcpy memcpy
+
+/*! Internal states of the HASH creation process */
+typedef enum _dcp_hash_algo_state
+{
+    kDCP_StateHashInit = 1u, /*!< Init state. */
+    kDCP_StateHashUpdate,    /*!< Update state. */
+} dcp_hash_algo_state_t;
+
+/*! multiple of 64-byte block represented as byte array of 32-bit words */
+typedef union _dcp_hash_block
+{
+    uint32_t w[DCP_HASH_BLOCK_SIZE / 4]; /*!< array of 32-bit words */
+    uint8_t b[DCP_HASH_BLOCK_SIZE];      /*!< byte array */
+} dcp_hash_block_t;
+
+/*! internal dcp_hash context structure */
+typedef struct _dcp_hash_ctx_internal
+{
+    dcp_hash_block_t blk;        /*!< memory buffer. only full blocks are written to DCP during hash updates */
+    size_t blksz;                /*!< number of valid bytes in memory buffer */
+    dcp_hash_algo_t algo;        /*!< selected algorithm from the set of supported algorithms */
+    dcp_hash_algo_state_t state; /*!< finite machine state of the hash software process */
+    uint32_t fullMessageSize;    /*!< track message size */
+    uint32_t ctrl0;              /*!< HASH_INIT and HASH_TERM flags */
+    uint32_t runningHash[9];     /*!< running hash. up to SHA-256 plus size, that is 36 bytes. */
+    dcp_handle_t *handle;
+} dcp_hash_ctx_internal_t;
+
+/*!< SHA-1/SHA-2 digest length in bytes  */
+enum _dcp_hash_digest_len
+{
+    kDCP_OutLenSha1   = 20u,
+    kDCP_OutLenSha256 = 32u,
+    kDCP_OutLenCrc32  = 4u,
+};
+
+enum _dcp_work_packet_bit_definitions
+{
+    kDCP_CONTROL0_DECR_SEMAPHOR      = 1u << 1,  /* DECR_SEMAPHOR */
+    kDCP_CONTROL0_ENABLE_HASH        = 1u << 6,  /* ENABLE_HASH */
+    kDCP_CONTROL0_HASH_INIT          = 1u << 12, /* HASH_INIT */
+    kDCP_CONTROL0_HASH_TERM          = 1u << 13, /* HASH_TERM */
+    kDCP_CONTROL1_HASH_SELECT_SHA256 = 2u << 16,
+    kDCP_CONTROL1_HASH_SELECT_SHA1   = 0u << 16,
+    kDCP_CONTROL1_HASH_SELECT_CRC32  = 1u << 16,
+};
+
+/*! 64-byte block represented as byte array of 16 32-bit words */
+typedef union _dcp_sha_block
+{
+    uint32_t w[64 / 4]; /*!< array of 32-bit words */
+    uint8_t b[64];      /*!< byte array */
+} dcp_sha_block_t;
+
+#if defined(DCP_HASH_CAVP_COMPATIBLE)
+/* result of sha1 hash for message with zero size */
+static uint8_t s_nullSha1[] = {0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 0x32, 0x55,
+                               0xbf, 0xef, 0x95, 0x60, 0x18, 0x90, 0xaf, 0xd8, 0x07, 0x09};
+/* result of sha256 hash for message with zero size */
+static uint8_t s_nullSha256[] = {0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 0x9a, 0xfb, 0xf4,
+                                 0xc8, 0x99, 0x6f, 0xb9, 0x24, 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b,
+                                 0x93, 0x4c, 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55};
+#endif /* DCP_HASH_CAVP_COMPATIBLE */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+AT_NONCACHEABLE_SECTION_INIT(static dcp_context_t s_dcpContextSwitchingBuffer);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len)
+{
+    for (uint32_t i = 0; i < src_len; i++)
+    {
+        dest[i] = src[src_len - 1U - i];
+    }
+}
+
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+static inline uint32_t *DCP_FindCacheLine(uint8_t *dcpWorkExt)
+{
+    while (0U != ((uint32_t)dcpWorkExt & ((uint32_t)FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1U)))
+    {
+        dcpWorkExt++;
+    }
+    return (uint32_t *)(uint32_t)dcpWorkExt;
+}
+#endif
+
+static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel)
+{
+    uint32_t statReg = 0;
+    uint32_t semaReg = 0;
+    status_t status  = kStatus_Fail;
+
+    switch (channel)
+    {
+        case kDCP_Channel0:
+            statReg = base->CH0STAT;
+            semaReg = base->CH0SEMA;
+            break;
+
+        case kDCP_Channel1:
+            statReg = base->CH1STAT;
+            semaReg = base->CH1SEMA;
+            break;
+
+        case kDCP_Channel2:
+            statReg = base->CH2STAT;
+            semaReg = base->CH2SEMA;
+            break;
+
+        case kDCP_Channel3:
+            statReg = base->CH3STAT;
+            semaReg = base->CH3SEMA;
+            break;
+
+        default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            break;
+    }
+
+    if (!((0U != (semaReg & DCP_CH0SEMA_VALUE_MASK)) || (0U != (statReg & DCP_CH0STAT_ERROR_CODE_MASK))))
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+static void dcp_clear_status(DCP_Type *base)
+{
+    volatile uint32_t *dcpStatClrPtr = (volatile uint32_t *)&base->STAT + 2u;
+    *dcpStatClrPtr                   = 0xFFu;
+
+    while ((base->STAT & 0xffu) != 0U)
+    {
+    }
+}
+
+static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask)
+{
+    volatile uint32_t *chStatClrPtr;
+
+    if (0U != (mask & (uint32_t)kDCP_Channel0))
+    {
+        chStatClrPtr  = &base->CH0STAT_CLR;
+        *chStatClrPtr = 0xFFu;
+    }
+    if (0U != (mask & (uint32_t)kDCP_Channel1))
+    {
+        chStatClrPtr  = &base->CH1STAT_CLR;
+        *chStatClrPtr = 0xFFu;
+    }
+    if (0U != (mask & (uint32_t)kDCP_Channel2))
+    {
+        chStatClrPtr  = &base->CH2STAT_CLR;
+        *chStatClrPtr = 0xFFu;
+    }
+    if (0U != (mask & (uint32_t)kDCP_Channel3))
+    {
+        chStatClrPtr  = &base->CH3STAT_CLR;
+        *chStatClrPtr = 0xFFu;
+    }
+}
+
+static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key)
+{
+    base->KEY = DCP_KEY_INDEX(handle->keySlot) | DCP_KEY_SUBWORD(0);
+    /* move the key by 32-bit words */
+    int i          = 0;
+    size_t keySize = 16u;
+    while (keySize != 0U)
+    {
+        keySize -= sizeof(uint32_t);
+        base->KEYDATA = ((uint32_t *)(uintptr_t)key)[i];
+        i++;
+    }
+    return kStatus_Success;
+}
+
+/* Disable optimizations for GCC to prevent instruction reordering */
+#if defined(__GNUC__)
+#pragma GCC push_options
+#pragma GCC optimize("O0")
+#endif
+static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket)
+{
+    status_t status;
+
+    /* check if our channel is active */
+    if ((base->STAT & (uint32_t)handle->channel) != (uint32_t)handle->channel)
+    {
+        /* disable global interrupt */
+        uint32_t currPriMask = DisableGlobalIRQ();
+
+        /* re-check if our channel is still available */
+        if ((base->STAT & (uint32_t)handle->channel) == 0U)
+        {
+            volatile uint32_t *cmdptr = NULL;
+            volatile uint32_t *chsema = NULL;
+
+            switch (handle->channel)
+            {
+                case kDCP_Channel0:
+                    cmdptr = &base->CH0CMDPTR;
+                    chsema = &base->CH0SEMA;
+                    break;
+
+                case kDCP_Channel1:
+                    cmdptr = &base->CH1CMDPTR;
+                    chsema = &base->CH1SEMA;
+                    break;
+
+                case kDCP_Channel2:
+                    cmdptr = &base->CH2CMDPTR;
+                    chsema = &base->CH2SEMA;
+                    break;
+
+                case kDCP_Channel3:
+                    cmdptr = &base->CH3CMDPTR;
+                    chsema = &base->CH3SEMA;
+                    break;
+
+                default:
+                    /* All the cases have been listed above, the default clause should not be reached. */
+                    break;
+            }
+
+            if ((NULL != cmdptr) && (NULL != chsema))
+            {
+                /* set out packet to DCP CMDPTR */
+                *cmdptr = (uint32_t)dcpPacket;
+
+#if defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+                /* Clean DCACHE before sending DCP packet to engine */
+                DCACHE_CleanByRange((uint32_t)dcpPacket, sizeof(dcp_work_packet_t));
+#endif
+                /* Make sure that all data memory accesses are completed before starting of the job */
+                __DSB();
+                __ISB();
+
+                /* set the channel semaphore to start the job */
+                *chsema = 1u;
+            }
+
+            status = kStatus_Success;
+        }
+
+        else
+        {
+            status = (int32_t)kStatus_DCP_Again;
+        }
+        /* global interrupt enable */
+        EnableGlobalIRQ(currPriMask);
+    }
+
+    else
+    {
+        return (int32_t)kStatus_DCP_Again;
+    }
+
+    return status;
+}
+#if defined(__GNUC__)
+#pragma GCC pop_options
+#endif
+
+/*!
+ * brief Set AES key to dcp_handle_t struct and optionally to DCP.
+ *
+ * Sets the AES key for encryption/decryption with the dcp_handle_t structure.
+ * The dcp_handle_t input argument specifies keySlot.
+ * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use
+ * status.
+ * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct.
+ * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2,
+ * kDCP_KeySlot3),
+ * this function will also load the supplied key to the specified keySlot in DCP.
+ *
+ * param   base DCP peripheral base address.
+ * param   handle Handle used for the request.
+ * param   key 0-mod-4 aligned pointer to AES key.
+ * param   keySize AES key size in bytes. Shall equal 16.
+ * return  status from set key operation
+ */
+status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize)
+{
+    status_t status = kStatus_Fail;
+
+    if ((kDCP_OtpKey == handle->keySlot) || (kDCP_OtpUniqueKey == handle->keySlot))
+    {
+        /* for AES OTP and unique key, check and return read from fuses status */
+        if ((base->STAT & DCP_STAT_OTP_KEY_READY_MASK) == DCP_STAT_OTP_KEY_READY_MASK)
+        {
+            status = kStatus_Success;
+        }
+    }
+    else
+    {
+        /* only work with aligned key[] */
+        if ((0x3U & (uintptr_t)key) != 0U)
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* keySize must be 16. */
+        if (keySize != 16U)
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* move the key by 32-bit words */
+        int i = 0;
+        while (keySize != 0U)
+        {
+            keySize -= sizeof(uint32_t);
+            handle->keyWord[i] = ((uint32_t *)(uintptr_t)key)[i];
+            i++;
+        }
+
+        if (kDCP_PayloadKey != handle->keySlot)
+        {
+            /* move the key by 32-bit words to DCP SRAM-based key storage */
+            status = dcp_aes_set_sram_based_key(base, handle, key);
+        }
+        else
+        {
+            /* for PAYLOAD_KEY, just return Ok status now */
+            status = kStatus_Success;
+        }
+    }
+
+    return status;
+}
+
+/*!
+ * brief Encrypts AES on one or multiple 128-bit block(s).
+ *
+ * Encrypts AES.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from encrypt operation
+ */
+status_t DCP_AES_EncryptEcb(
+    DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size)
+{
+    status_t completionStatus = kStatus_Fail;
+
+    /* Use extended  DCACHE line size aligned structure */
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    dcp_work_packet_t *dcpWork;
+    uint8_t dcpWorkExt[sizeof(dcp_work_packet_t) + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE] = {0U};
+    dcpWork = (dcp_work_packet_t *)(uint32_t)DCP_FindCacheLine(dcpWorkExt);
+#else
+    dcp_work_packet_t dcpWorkPacket = {0};
+    dcp_work_packet_t *dcpWork      = &dcpWorkPacket;
+#endif
+
+    do
+    {
+        completionStatus = DCP_AES_EncryptEcbNonBlocking(base, handle, dcpWork, plaintext, ciphertext, size);
+    } while (completionStatus == (int32_t)kStatus_DCP_Again);
+
+    if (completionStatus != kStatus_Success)
+    {
+        return completionStatus;
+    }
+
+    return DCP_WaitForChannelComplete(base, handle);
+}
+
+/*!
+ * brief Encrypts AES using the ECB block mode.
+ *
+ * Puts AES ECB encrypt work packet to DCP channel.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param plaintext Input plain text to encrypt.
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *plaintext,
+                                       uint8_t *ciphertext,
+                                       size_t size)
+{
+    /* Size must be 16-byte multiple */
+    if ((size < 16u) || (0U != (size % 16u)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    dcpPacket->control0 =
+        0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->sourceBufferAddress      = (uint32_t)plaintext;
+    dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
+    dcpPacket->bufferSize               = (uint32_t)size;
+
+    if (handle->keySlot == kDCP_OtpKey)
+    {
+        dcpPacket->control0 |= ((uint32_t)1u << 10);  /* OTP_KEY */
+        dcpPacket->control1 = ((uint32_t)0xFFu << 8); /* KEY_SELECT = OTP_KEY */
+    }
+    else if (handle->keySlot == kDCP_OtpUniqueKey)
+    {
+        dcpPacket->control0 |= ((uint32_t)1u << 10);  /* OTP_KEY */
+        dcpPacket->control1 = ((uint32_t)0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */
+    }
+    else if (handle->keySlot == kDCP_PayloadKey)
+    {
+        /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */
+        dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0];
+        dcpPacket->control0 |= ((uint32_t)1u << 11); /* PAYLOAD_KEY */
+    }
+    else
+    {
+        dcpPacket->control1 = ((uint32_t)handle->keySlot << 8); /* KEY_SELECT = keySlot */
+    }
+
+    return dcp_schedule_work(base, handle, dcpPacket);
+}
+
+/*!
+ * brief Decrypts AES on one or multiple 128-bit block(s).
+ *
+ * Decrypts AES.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param ciphertext Input plain text to encrypt
+ * param[out] plaintext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from decrypt operation
+ */
+status_t DCP_AES_DecryptEcb(
+    DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size)
+{
+    status_t completionStatus = kStatus_Fail;
+
+    /* Use extended  DCACHE line size aligned structure */
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    dcp_work_packet_t *dcpWork;
+    uint8_t dcpWorkExt[sizeof(dcp_work_packet_t) + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE] = {0U};
+    dcpWork = (dcp_work_packet_t *)(uint32_t)DCP_FindCacheLine(dcpWorkExt);
+#else
+    dcp_work_packet_t dcpWorkPacket = {0};
+    dcp_work_packet_t *dcpWork      = &dcpWorkPacket;
+#endif
+
+    do
+    {
+        completionStatus = DCP_AES_DecryptEcbNonBlocking(base, handle, dcpWork, ciphertext, plaintext, size);
+    } while (completionStatus == (int32_t)(kStatus_DCP_Again));
+
+    if (completionStatus != kStatus_Success)
+    {
+        return completionStatus;
+    }
+
+    return DCP_WaitForChannelComplete(base, handle);
+}
+
+/*!
+ * brief Decrypts AES using ECB block mode.
+ *
+ * Puts AES ECB decrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *ciphertext,
+                                       uint8_t *plaintext,
+                                       size_t size)
+{
+    /* Size must be 16-byte multiple */
+    if ((size < 16u) || (0U != (size % 16u)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    dcpPacket->control0                 = 0x22u | (handle->swapConfig & 0xFC0000u); /* ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->sourceBufferAddress      = (uint32_t)ciphertext;
+    dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
+    dcpPacket->bufferSize               = (uint32_t)size;
+
+    if (handle->keySlot == kDCP_OtpKey)
+    {
+        dcpPacket->control0 |= ((uint32_t)1u << 10);  /* OTP_KEY */
+        dcpPacket->control1 = ((uint32_t)0xFFu << 8); /* KEY_SELECT = OTP_KEY */
+    }
+    else if (handle->keySlot == kDCP_OtpUniqueKey)
+    {
+        dcpPacket->control0 |= ((uint32_t)1u << 10);  /* OTP_KEY */
+        dcpPacket->control1 = ((uint32_t)0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */
+    }
+    else if (handle->keySlot == kDCP_PayloadKey)
+    {
+        /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */
+        dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0];
+        dcpPacket->control0 |= ((uint32_t)1u << 11); /* PAYLOAD_KEY */
+    }
+    else
+    {
+        dcpPacket->control1 = ((uint32_t)handle->keySlot << 8); /* KEY_SELECT = keySlot */
+    }
+
+    return dcp_schedule_work(base, handle, dcpPacket);
+}
+
+/*!
+ * brief Encrypts AES using CBC block mode.
+ *
+ * Encrypts AES using CBC block mode.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return Status from encrypt operation
+ */
+status_t DCP_AES_EncryptCbc(DCP_Type *base,
+                            dcp_handle_t *handle,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            size_t size,
+                            const uint8_t iv[16])
+{
+    status_t completionStatus = kStatus_Fail;
+
+    /* Use extended  DCACHE line size aligned structure */
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    dcp_work_packet_t *dcpWork;
+    uint8_t dcpWorkExt[sizeof(dcp_work_packet_t) + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE] = {0U};
+    dcpWork = (dcp_work_packet_t *)(uint32_t)DCP_FindCacheLine(dcpWorkExt);
+#else
+    dcp_work_packet_t dcpWorkPacket = {0};
+    dcp_work_packet_t *dcpWork      = &dcpWorkPacket;
+#endif
+
+    do
+    {
+        completionStatus = DCP_AES_EncryptCbcNonBlocking(base, handle, dcpWork, plaintext, ciphertext, size, iv);
+    } while (completionStatus == (int32_t)kStatus_DCP_Again);
+
+    if (completionStatus != kStatus_Success)
+    {
+        return completionStatus;
+    }
+
+    return DCP_WaitForChannelComplete(base, handle);
+}
+
+/*!
+ * brief Encrypts AES using CBC block mode.
+ *
+ * Puts AES CBC encrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request. Specifies jobRing.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *plaintext,
+                                       uint8_t *ciphertext,
+                                       size_t size,
+                                       const uint8_t *iv)
+{
+    /* Size must be 16-byte multiple */
+    if ((size < 16u) || (0U != (size % 16u)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    dcpPacket->control0 =
+        0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control1                 = 0x10u;   /* CBC */
+    dcpPacket->sourceBufferAddress      = (uint32_t)plaintext;
+    dcpPacket->destinationBufferAddress = (uint32_t)ciphertext;
+    dcpPacket->bufferSize               = (uint32_t)size;
+
+    if (handle->keySlot == kDCP_OtpKey)
+    {
+        dcpPacket->payloadPointer = (uint32_t)iv;
+        dcpPacket->control0 |= ((uint32_t)1u << 10);   /* OTP_KEY */
+        dcpPacket->control1 |= ((uint32_t)0xFFu << 8); /* KEY_SELECT = OTP_KEY */
+    }
+    else if (handle->keySlot == kDCP_OtpUniqueKey)
+    {
+        dcpPacket->payloadPointer = (uint32_t)iv;
+        dcpPacket->control0 |= ((uint32_t)1u << 10);   /* OTP_KEY */
+        dcpPacket->control1 |= ((uint32_t)0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */
+    }
+    else if (handle->keySlot == kDCP_PayloadKey)
+    {
+        /* In this case payload must contain key & iv in one array. */
+        /* Copy iv into handle right behind the keyWord[] so we can point payload to keyWord[]. */
+        (void)dcp_memcpy(handle->iv, (const uint32_t *)(uintptr_t)iv, 16);
+        dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0];
+        dcpPacket->control0 |= ((uint32_t)1u << 11); /* PAYLOAD_KEY */
+    }
+    else
+    {
+        dcpPacket->payloadPointer = (uint32_t)iv;
+        dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT = keySlot */
+    }
+
+    return dcp_schedule_work(base, handle, dcpPacket);
+}
+
+/*!
+ * brief Decrypts AES using CBC block mode.
+ *
+ * Decrypts AES using CBC block mode.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return Status from decrypt operation
+ */
+status_t DCP_AES_DecryptCbc(DCP_Type *base,
+                            dcp_handle_t *handle,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            size_t size,
+                            const uint8_t iv[16])
+{
+    status_t completionStatus = kStatus_Fail;
+
+    /* Use extended  DCACHE line size aligned structure */
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    dcp_work_packet_t *dcpWork;
+    uint8_t dcpWorkExt[sizeof(dcp_work_packet_t) + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE] = {0U};
+    dcpWork = (dcp_work_packet_t *)(uint32_t)DCP_FindCacheLine(dcpWorkExt);
+#else
+    dcp_work_packet_t dcpWorkPacket = {0};
+    dcp_work_packet_t *dcpWork      = &dcpWorkPacket;
+#endif
+
+    do
+    {
+        completionStatus = DCP_AES_DecryptCbcNonBlocking(base, handle, dcpWork, ciphertext, plaintext, size, iv);
+    } while (completionStatus == (int32_t)kStatus_DCP_Again);
+
+    if (completionStatus != (int32_t)kStatus_Success)
+    {
+        return completionStatus;
+    }
+
+    return DCP_WaitForChannelComplete(base, handle);
+}
+
+/*!
+ * brief Decrypts AES using CBC block mode.
+ *
+ * Puts AES CBC decrypt dcpPacket to DCP input job ring.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for this request. Specifies jobRing.
+ * param[out] dcpPacket Memory for the DCP work packet.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * return kStatus_Success The work packet has been scheduled at DCP channel.
+ * return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *ciphertext,
+                                       uint8_t *plaintext,
+                                       size_t size,
+                                       const uint8_t *iv)
+{
+    /* Size must be 16-byte multiple */
+    if ((size < 16u) || (0U != (size % 16u)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */
+    dcpPacket->control1 = 0x10u;                                     /* CBC */
+    dcpPacket->sourceBufferAddress      = (uint32_t)ciphertext;
+    dcpPacket->destinationBufferAddress = (uint32_t)plaintext;
+    dcpPacket->bufferSize               = (uint32_t)size;
+
+    if (handle->keySlot == kDCP_OtpKey)
+    {
+        dcpPacket->payloadPointer = (uint32_t)iv;
+        dcpPacket->control0 |= ((uint32_t)1u << 10);   /* OTP_KEY */
+        dcpPacket->control1 |= ((uint32_t)0xFFu << 8); /* OTP_KEY */
+    }
+    else if (handle->keySlot == kDCP_OtpUniqueKey)
+    {
+        dcpPacket->payloadPointer = (uint32_t)iv;
+        dcpPacket->control0 |= ((uint32_t)1u << 10);   /* OTP_KEY */
+        dcpPacket->control1 |= ((uint32_t)0xFEu << 8); /* UNIQUE_KEY */
+    }
+    else if (handle->keySlot == kDCP_PayloadKey)
+    {
+        /* in this case payload must contain KEY + IV together */
+        /* copy iv into handle struct so we can point payload directly to keyWord[]. */
+        (void)dcp_memcpy(handle->iv, (const uint32_t *)(uintptr_t)iv, 16);
+        dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0];
+        dcpPacket->control0 |= ((uint32_t)1u << 11); /* PAYLOAD_KEY */
+    }
+    else
+    {
+        dcpPacket->payloadPointer = (uint32_t)iv;
+        dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT */
+    }
+
+    return dcp_schedule_work(base, handle, dcpPacket);
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the DCP configuration structure to a default value. The default
+ * values are as follows.
+ *   dcpConfig->gatherResidualWrites = true;
+ *   dcpConfig->enableContextCaching = true;
+ *   dcpConfig->enableContextSwitching = true;
+ *   dcpConfig->enableChannnel = kDCP_chEnableAll;
+ *   dcpConfig->enableChannelInterrupt = kDCP_chIntDisable;
+ *
+ * param[out] config Pointer to configuration structure.
+ */
+void DCP_GetDefaultConfig(dcp_config_t *config)
+{
+    /* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses
+     * dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support
+     * Hash context switch (different messages interleaved) on the same channel.
+     */
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    dcp_config_t userConfig = {
+        true, false, true, (uint8_t)kDCP_chEnableAll, (uint8_t)kDCP_chIntDisable,
+    };
+
+    *config = userConfig;
+}
+
+/*!
+ * brief   Enables clock to and enables DCP
+ *
+ * Enable DCP clock and configure DCP.
+ *
+ * param base DCP base address
+ * param config Pointer to configuration structure.
+ */
+void DCP_Init(DCP_Type *base, const dcp_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_Dcp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    base->CTRL = 0xF0800000u; /* reset value */
+    base->CTRL = 0x30800000u; /* default value */
+
+    dcp_clear_status(base);
+    dcp_clear_channel_status(
+        base, (uint32_t)kDCP_Channel0 | (uint32_t)kDCP_Channel1 | (uint32_t)kDCP_Channel2 | (uint32_t)kDCP_Channel3);
+
+    base->CTRL = DCP_CTRL_GATHER_RESIDUAL_WRITES(config->gatherResidualWrites) |
+                 DCP_CTRL_ENABLE_CONTEXT_CACHING(config->enableContextCaching) |
+                 DCP_CTRL_ENABLE_CONTEXT_SWITCHING(config->enableContextSwitching) |
+                 DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(config->enableChannelInterrupt);
+
+    /* enable DCP channels */
+    base->CHANNELCTRL = DCP_CHANNELCTRL_ENABLE_CHANNEL(config->enableChannel);
+
+    /* use context switching buffer */
+    base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer;
+}
+
+/*!
+ * brief   Disable DCP clock
+ *
+ * Reset DCP and Disable DCP clock.
+ *
+ * param base DCP base address
+ */
+void DCP_Deinit(DCP_Type *base)
+{
+    base->CTRL = 0xF0800000u; /* reset value */
+    (void)memset(&s_dcpContextSwitchingBuffer, 0, sizeof(s_dcpContextSwitchingBuffer));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(kCLOCK_Dcp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Poll and wait on DCP channel.
+ *
+ * Polls the specified DCP channel until current it completes activity.
+ *
+ * param   base DCP peripheral base address.
+ * param   handle Specifies DCP channel.
+ * return  kStatus_Success When data processing completes without error.
+ * return  kStatus_Fail When error occurs.
+ */
+status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle)
+{
+    /* wait if our channel is still active */
+    while ((base->STAT & (uint32_t)handle->channel) == (uint32_t)handle->channel)
+    {
+    }
+
+    if (dcp_get_channel_status(base, handle->channel) != kStatus_Success)
+    {
+        dcp_clear_status(base);
+        dcp_clear_channel_status(base, (uint32_t)handle->channel);
+        return kStatus_Fail;
+    }
+
+    dcp_clear_status(base);
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Check validity of algoritm.
+ *
+ * This function checks the validity of input argument.
+ *
+ * @param algo Tested algorithm value.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t dcp_hash_check_input_alg(dcp_hash_algo_t algo)
+{
+    if ((algo != kDCP_Sha256) && (algo != kDCP_Sha1) && (algo != kDCP_Crc32))
+    {
+        return kStatus_InvalidArgument;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Check validity of input arguments.
+ *
+ * This function checks the validity of input arguments.
+ *
+ * @param base DCP peripheral base address.
+ * @param ctx Memory buffer given by user application where the DCP_HASH_Init/DCP_HASH_Update/DCP_HASH_Finish store
+ * context.
+ * @param algo Tested algorithm value.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t dcp_hash_check_input_args(DCP_Type *base, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
+{
+    /* Check validity of input algorithm */
+    if (kStatus_Success != dcp_hash_check_input_alg(algo))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if ((NULL == ctx) || (NULL == base))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Check validity of internal software context.
+ *
+ * This function checks if the internal context structure looks correct.
+ *
+ * @param ctxInternal Internal context.
+ * @param message Input message address.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t dcp_hash_check_context(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message)
+{
+    if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != dcp_hash_check_input_alg(ctxInternal->algo)))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Initialize the SHA engine for new hash.
+ *
+ * This function sets kDCP_CONTROL0_HASH_INIT for control0 in work packet to start a new hash.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ */
+static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal)
+{
+    status_t status;
+
+    status = kStatus_InvalidArgument;
+
+    if ((kDCP_Sha256 == ctxInternal->algo) || (kDCP_Sha1 == ctxInternal->algo) || (kDCP_Crc32 == ctxInternal->algo))
+    {
+        ctxInternal->ctrl0 = (uint32_t)kDCP_CONTROL0_HASH_INIT;
+        status             = kStatus_Success;
+    }
+
+    return status;
+}
+
+static status_t dcp_hash_update_non_blocking(
+    DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
+{
+    dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) |
+                          (uint32_t)kDCP_CONTROL0_ENABLE_HASH | (uint32_t)kDCP_CONTROL0_DECR_SEMAPHOR;
+    if (ctxInternal->algo == kDCP_Sha256)
+    {
+        dcpPacket->control1 = (uint32_t)kDCP_CONTROL1_HASH_SELECT_SHA256;
+    }
+    else if (ctxInternal->algo == kDCP_Sha1)
+    {
+        dcpPacket->control1 = (uint32_t)kDCP_CONTROL1_HASH_SELECT_SHA1;
+    }
+    else if (ctxInternal->algo == kDCP_Crc32)
+    {
+        /* In CRC-32 case if size is zero, do not schedule other computing */
+        if (size == 0U)
+        {
+#if defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+            /* Clear DCACHE memory before starting the engine */
+            DCACHE_CleanByRange((uint32_t)ctxInternal, sizeof(dcp_hash_ctx_internal_t));
+#endif
+            /* Make sure that all data memory accesses are completed before starting of the job */
+            __DSB();
+            __ISB();
+            return kStatus_Success;
+        }
+        dcpPacket->control1 = (uint32_t)kDCP_CONTROL1_HASH_SELECT_CRC32;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+    dcpPacket->sourceBufferAddress      = (uint32_t)msg;
+    dcpPacket->destinationBufferAddress = 0;
+    dcpPacket->bufferSize               = size;
+    dcpPacket->payloadPointer           = (uint32_t)ctxInternal->runningHash;
+
+#if defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    /* Clear DCACHE memory before starting the engine */
+    DCACHE_CleanByRange((uint32_t)ctxInternal, sizeof(dcp_hash_ctx_internal_t));
+#endif
+    /* Make sure that all data memory accesses are completed before starting of the job */
+    __DSB();
+    __ISB();
+
+    return dcp_schedule_work(base, ctxInternal->handle, dcpPacket);
+}
+
+static status_t dcp_hash_update(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size)
+{
+    status_t completionStatus = kStatus_Fail;
+
+    /* Use extended  DCACHE line size aligned structure */
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    dcp_work_packet_t *dcpWork;
+    uint8_t dcpWorkExt[sizeof(dcp_work_packet_t) + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE] = {0U};
+    dcpWork = (dcp_work_packet_t *)(uint32_t)DCP_FindCacheLine(dcpWorkExt);
+#else
+    dcp_work_packet_t dcpWorkPacket = {0};
+    dcp_work_packet_t *dcpWork      = &dcpWorkPacket;
+#endif
+
+    do
+    {
+        completionStatus = dcp_hash_update_non_blocking(base, ctxInternal, dcpWork, msg, size);
+    } while (completionStatus == (int32_t)kStatus_DCP_Again);
+
+    completionStatus = DCP_WaitForChannelComplete(base, ctxInternal->handle);
+
+    ctxInternal->ctrl0 = 0; /* clear kDCP_CONTROL0_HASH_INIT and kDCP_CONTROL0_HASH_TERM flags */
+    return (completionStatus);
+}
+
+/*!
+ * @brief Adds message to current hash.
+ *
+ * This function merges the message to fill the internal buffer, empties the internal buffer if
+ * it becomes full, then process all remaining message data.
+ *
+ *
+ * @param base DCP peripheral base address.
+ * @param ctxInternal Internal context.
+ * @param message Input message.
+ * @param messageSize Size of input message in bytes.
+ * @return kStatus_Success.
+ */
+static status_t dcp_hash_process_message_data(DCP_Type *base,
+                                              dcp_hash_ctx_internal_t *ctxInternal,
+                                              const uint8_t *message,
+                                              size_t messageSize)
+{
+    status_t status = kStatus_Fail;
+
+    /* if there is partially filled internal buffer, fill it to full block */
+    if (ctxInternal->blksz > 0U)
+    {
+        size_t toCopy = DCP_HASH_BLOCK_SIZE - ctxInternal->blksz;
+        (void)dcp_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy);
+        message += toCopy;
+        messageSize -= toCopy;
+
+        /* process full internal block */
+        status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], DCP_HASH_BLOCK_SIZE);
+        if (kStatus_Success != status)
+        {
+            return status;
+        }
+    }
+
+    /* process all full blocks in message[] */
+    uint32_t fullBlocksSize = ((messageSize >> 6) << 6); /* (X / 64) * 64 */
+    if (fullBlocksSize > 0U)
+    {
+        status = dcp_hash_update(base, ctxInternal, message, fullBlocksSize);
+        if (kStatus_Success != status)
+        {
+            return status;
+        }
+        message += fullBlocksSize;
+        messageSize -= fullBlocksSize;
+    }
+
+    /* copy last incomplete message bytes into internal block */
+    (void)dcp_memcpy(&ctxInternal->blk.b[0], message, messageSize);
+    ctxInternal->blksz = messageSize;
+
+    return status;
+}
+
+/*!
+ * @brief Finalize the running hash to make digest.
+ *
+ * This function empties the internal buffer, adds padding bits, and generates final digest.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ * @return kStatus_Success.
+ */
+static status_t dcp_hash_finalize(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal)
+{
+    status_t status;
+
+    ctxInternal->ctrl0 |= (uint32_t)kDCP_CONTROL0_HASH_TERM;
+    status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], ctxInternal->blksz);
+
+    return status;
+}
+
+static void dcp_hash_save_running_hash(dcp_hash_ctx_internal_t *ctxInternal)
+{
+    uint32_t *srcAddr = NULL;
+
+    switch (ctxInternal->handle->channel)
+    {
+        case kDCP_Channel0:
+            srcAddr = &s_dcpContextSwitchingBuffer.x[43];
+            break;
+
+        case kDCP_Channel1:
+            srcAddr = &s_dcpContextSwitchingBuffer.x[30];
+            break;
+
+        case kDCP_Channel2:
+            srcAddr = &s_dcpContextSwitchingBuffer.x[17];
+            break;
+
+        case kDCP_Channel3:
+            srcAddr = &s_dcpContextSwitchingBuffer.x[4];
+            break;
+
+        default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            break;
+    }
+    if (srcAddr != NULL)
+    {
+        DCACHE_InvalidateByRange((uint32_t)srcAddr, sizeof(ctxInternal->runningHash));
+        (void)dcp_memcpy(ctxInternal->runningHash, srcAddr, sizeof(ctxInternal->runningHash));
+    }
+}
+
+static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal)
+{
+    uint32_t *destAddr = NULL;
+
+    switch (ctxInternal->handle->channel)
+    {
+        case kDCP_Channel0:
+            destAddr = &s_dcpContextSwitchingBuffer.x[43];
+            break;
+
+        case kDCP_Channel1:
+            destAddr = &s_dcpContextSwitchingBuffer.x[30];
+            break;
+
+        case kDCP_Channel2:
+            destAddr = &s_dcpContextSwitchingBuffer.x[17];
+            break;
+
+        case kDCP_Channel3:
+            destAddr = &s_dcpContextSwitchingBuffer.x[4];
+            break;
+
+        default:
+            /* No valid channel */
+            break;
+    }
+    if (destAddr != NULL)
+    {
+        (void)dcp_memcpy(destAddr, ctxInternal->runningHash, sizeof(ctxInternal->runningHash));
+    }
+}
+
+/*!
+ * brief Initialize HASH context
+ *
+ * This function initializes the HASH.
+ *
+ * param base DCP peripheral base address
+ * param handle Specifies the DCP channel used for hashing.
+ * param[out] ctx Output hash context
+ * param algo Underlaying algorithm to use for hash computation.
+ * return Status of initialization
+ */
+status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
+{
+    status_t status;
+
+    dcp_hash_ctx_internal_t *ctxInternal;
+    /* Align structure on DCACHE line*/
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    ctxInternal = (dcp_hash_ctx_internal_t *)(uint32_t)((uint8_t *)ctx + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE);
+#else
+    ctxInternal                     = (dcp_hash_ctx_internal_t *)(uint32_t)ctx;
+#endif
+
+    /* compile time check for the correct structure size */
+    BUILD_ASSURE(sizeof(dcp_hash_ctx_t) >= sizeof(dcp_hash_ctx_internal_t), dcp_hash_ctx_t_size);
+    uint32_t i;
+
+    status = dcp_hash_check_input_args(base, ctx, algo);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* set algorithm in context struct for later use */
+    ctxInternal->algo  = algo;
+    ctxInternal->blksz = 0u;
+
+    const uint32_t j = sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]);
+    for (i = 0; i < j; i++)
+    {
+        ctxInternal->blk.w[i] = 0u;
+    }
+    ctxInternal->state           = kDCP_StateHashInit;
+    ctxInternal->fullMessageSize = 0;
+    ctxInternal->handle          = handle;
+    return status;
+}
+
+/*!
+ * brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed. The functions blocks. If it returns kStatus_Success, the running hash
+ * has been updated (DCP has processed the input data), so the memory at ref input pointer
+ * can be released back to system. The DCP context buffer is updated with the running hash
+ * and with all necessary information to support possible context switch.
+ *
+ * param base DCP peripheral base address
+ * param[in,out] ctx HASH context
+ * param input Input data
+ * param inputSize Size of input data in bytes
+ * return Status of the hash update operation
+ */
+status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
+{
+    bool isUpdateState;
+    status_t status;
+    dcp_hash_ctx_internal_t *ctxInternal;
+    size_t blockSize;
+
+    /* Align structure on DCACHE line*/
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    ctxInternal = (dcp_hash_ctx_internal_t *)(uint32_t)((uint8_t *)ctx + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE);
+#else
+    ctxInternal                     = (dcp_hash_ctx_internal_t *)(uint32_t)ctx;
+#endif
+
+    if (inputSize == 0U)
+    {
+        return kStatus_Success;
+    }
+
+    status = dcp_hash_check_context(ctxInternal, input);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    ctxInternal->fullMessageSize += inputSize;
+    blockSize = DCP_HASH_BLOCK_SIZE;
+    /* if we are still less than DCP_HASH_BLOCK_SIZE bytes, keep only in context */
+    if ((ctxInternal->blksz + inputSize) <= blockSize)
+    {
+        (void)dcp_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize);
+        ctxInternal->blksz += inputSize;
+        return status;
+    }
+    else
+    {
+        isUpdateState = ctxInternal->state == kDCP_StateHashUpdate;
+        if (!isUpdateState)
+        {
+            /* start NEW hash */
+            status = dcp_hash_engine_init(base, ctxInternal);
+            if (status != kStatus_Success)
+            {
+                return status;
+            }
+            ctxInternal->state = kDCP_StateHashUpdate;
+        }
+        else
+        {
+            dcp_hash_restore_running_hash(ctxInternal);
+        }
+    }
+
+    /* process input data */
+    status = dcp_hash_process_message_data(base, ctxInternal, input, inputSize);
+    dcp_hash_save_running_hash(ctxInternal);
+    return status;
+}
+
+/*!
+ * brief Finalize hashing
+ *
+ * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context.
+ *
+ * param[in,out] ctx Input hash context
+ * param[out] output Output hash data
+ * param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
+ * output[] buffer. On function return, it stores the number of updated output bytes.
+ * return Status of the hash finish operation
+ */
+status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize)
+{
+    size_t algOutSize = 0;
+    status_t status;
+    dcp_hash_ctx_internal_t *ctxInternal;
+
+    /* Align structure on DCACHE line*/
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) && defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    ctxInternal = (dcp_hash_ctx_internal_t *)(uint32_t)((uint8_t *)ctx + FSL_FEATURE_L1DCACHE_LINESIZE_BYTE);
+#else
+    ctxInternal                     = (dcp_hash_ctx_internal_t *)(uint32_t)ctx;
+#endif
+
+    status = dcp_hash_check_context(ctxInternal, output);
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    if (ctxInternal->state == kDCP_StateHashInit)
+    {
+        status = dcp_hash_engine_init(base, ctxInternal);
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+    }
+    else
+    {
+        dcp_hash_restore_running_hash(ctxInternal);
+    }
+
+    size_t outSize = 0u;
+
+    /* compute algorithm output length */
+    switch (ctxInternal->algo)
+    {
+        case kDCP_Sha256:
+            outSize = (uint32_t)kDCP_OutLenSha256;
+            break;
+        case kDCP_Sha1:
+            outSize = (uint32_t)kDCP_OutLenSha1;
+            break;
+        case kDCP_Crc32:
+            outSize = (uint32_t)kDCP_OutLenCrc32;
+            break;
+        default:
+            /* All the cases have been listed above, the default clause should not be reached. */
+            break;
+    }
+    algOutSize = outSize;
+
+#if defined(DCP_HASH_CAVP_COMPATIBLE)
+    if (ctxInternal->fullMessageSize == 0U)
+    {
+        switch (ctxInternal->algo)
+        {
+            case kDCP_Sha256:
+                (void)dcp_memcpy(&output[0], &s_nullSha256, 32);
+                break;
+            case kDCP_Sha1:
+                (void)dcp_memcpy(&output[0], &s_nullSha1, 20);
+                break;
+            default:
+                /* All the cases have been listed above, the default clause should not be reached. */
+                break;
+        }
+
+        return kStatus_Success;
+    }
+#endif /* DCP_HASH_CAVP_COMPATIBLE */
+
+    /* flush message last incomplete block, if there is any, and add padding bits */
+    status = dcp_hash_finalize(base, ctxInternal);
+
+    if (outputSize != NULL)
+    {
+        if (algOutSize < *outputSize)
+        {
+            *outputSize = algOutSize;
+        }
+        else
+        {
+            algOutSize = *outputSize;
+        }
+    }
+
+#if defined(DCP_USE_DCACHE) && (DCP_USE_DCACHE == 1U)
+    DCACHE_InvalidateByRange((uint32_t)ctxInternal->runningHash, sizeof(ctxInternal->runningHash));
+#endif
+    /* Reverse and copy result to output[] */
+    dcp_reverse_and_copy((uint8_t *)ctxInternal->runningHash, &output[0], algOutSize);
+
+    (void)memset(ctx, 0, sizeof(dcp_hash_ctx_t));
+    return status;
+}
+
+/*!
+ * brief Create HASH on given data
+ *
+ * Perform the full SHA or CRC32 in one function call. The function is blocking.
+ *
+ * param base DCP peripheral base address
+ * param handle Handle used for the request.
+ * param algo Underlaying algorithm to use for hash computation.
+ * param input Input data
+ * param inputSize Size of input data in bytes
+ * param[out] output Output hash data
+ * param[out] outputSize Output parameter storing the size of the output hash in bytes
+ * return Status of the one call hash operation.
+ */
+status_t DCP_HASH(DCP_Type *base,
+                  dcp_handle_t *handle,
+                  dcp_hash_algo_t algo,
+                  const uint8_t *input,
+                  size_t inputSize,
+                  uint8_t *output,
+                  size_t *outputSize)
+{
+    dcp_hash_ctx_t hashCtx = {0};
+    status_t status;
+
+    status = DCP_HASH_Init(base, handle, &hashCtx, algo);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = DCP_HASH_Update(base, &hashCtx, input, inputSize);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = DCP_HASH_Finish(base, &hashCtx, output, outputSize);
+
+    return status;
+}
diff --git a/nxp/drivers/fsl_dcp.h b/nxp/drivers/fsl_dcp.h
new file mode 100644
index 0000000..b31944d
--- /dev/null
+++ b/nxp/drivers/fsl_dcp.h
@@ -0,0 +1,580 @@
+/*
+ * Copyright 2017-2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_DCP_H_
+#define _FSL_DCP_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*!
+ * @addtogroup dcp_driver
+ * @{
+ */
+/*! @name Driver version */
+/*@{*/
+/*! @brief DCP driver version. Version 2.1.6.
+ *
+ * Current version: 2.1.6
+ *
+ * Change log:
+ *
+ * - Version 2.1.6
+ *  - Bug Fix
+ *   - MISRA C-2012 issue fix.
+ *
+ * - Version 2.1.5
+ *  - Improvements
+ *   - Add support for DCACHE.
+ *
+ * - Version 2.1.4
+ *  - Bug Fix
+ *   - Fix CRC-32 computation issue on the code's block boundary size.
+ *
+ * - Version 2.1.3
+ *  - Bug Fix
+ *   - MISRA C-2012 issue fixed: rule 10.1, 10.3, 10.4, 11.9, 14.4, 16.4 and 17.7.
+ *
+ * - Version 2.1.2
+ *   - Fix sign-compare warning in dcp_reverse_and_copy.
+ *
+ * - Version 2.1.1
+ *   - Add DCP status clearing when channel operation is complete
+ *
+ * - 2.1.0
+ *   - Add byte/word swap feature for key, input and output data
+ *
+ * - Version 2.0.0
+ *   - Initial version
+ */
+#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 1, 6))
+/*@}*/
+
+/*! @brief DCP status return codes. */
+enum _dcp_status
+{
+    kStatus_DCP_Again = MAKE_STATUS(kStatusGroup_DCP, 0), /*!< Non-blocking function shall be called again. */
+};
+
+/*! @brief DCP channel enable.
+ *
+ */
+typedef enum _dcp_ch_enable
+{
+    kDCP_chDisable   = 0U,  /*!< DCP channel disable */
+    kDCP_ch0Enable   = 1U,  /*!< DCP channel 0 enable */
+    kDCP_ch1Enable   = 2U,  /*!< DCP channel 1 enable */
+    kDCP_ch2Enable   = 4U,  /*!< DCP channel 2 enable */
+    kDCP_ch3Enable   = 8U,  /*!< DCP channel 3 enable */
+    kDCP_chEnableAll = 15U, /*!< DCP channel enable all */
+} _dcp_ch_enable_t;
+
+/*! @brief DCP interrupt enable.
+ *
+ */
+typedef enum _dcp_ch_int_enable
+{
+    kDCP_chIntDisable = 0U, /*!< DCP interrupts disable */
+    kDCP_ch0IntEnable = 1U, /*!< DCP channel 0 interrupt enable */
+    kDCP_ch1IntEnable = 2U, /*!< DCP channel 1 interrupt enable */
+    kDCP_ch2IntEnable = 4U, /*!< DCP channel 2 interrupt enable */
+    kDCP_ch3IntEnable = 8U, /*!< DCP channel 3 interrupt enable */
+} _dcp_ch_int_enable_t;
+
+/*! @brief DCP channel selection.
+ *
+ */
+typedef enum _dcp_channel
+{
+    kDCP_Channel0 = (1u << 16), /*!< DCP channel 0. */
+    kDCP_Channel1 = (1u << 17), /*!< DCP channel 1. */
+    kDCP_Channel2 = (1u << 18), /*!< DCP channel 2. */
+    kDCP_Channel3 = (1u << 19), /*!< DCP channel 3. */
+} dcp_channel_t;
+
+/*! @brief DCP key slot selection.
+ *
+ */
+typedef enum _dcp_key_slot
+{
+    kDCP_KeySlot0     = 0U, /*!< DCP key slot 0. */
+    kDCP_KeySlot1     = 1U, /*!< DCP key slot 1. */
+    kDCP_KeySlot2     = 2U, /*!< DCP key slot 2.*/
+    kDCP_KeySlot3     = 3U, /*!< DCP key slot 3. */
+    kDCP_OtpKey       = 4U, /*!< DCP OTP key. */
+    kDCP_OtpUniqueKey = 5U, /*!< DCP unique OTP key. */
+    kDCP_PayloadKey   = 6U, /*!< DCP payload key. */
+} dcp_key_slot_t;
+
+/*! @brief DCP key, input & output swap options
+ *
+ */
+typedef enum _dcp_swap
+{
+    kDCP_NoSwap         = 0x0U,
+    kDCP_KeyByteSwap    = 0x40000U,
+    kDCP_KeyWordSwap    = 0x80000U,
+    kDCP_InputByteSwap  = 0x100000U,
+    kDCP_InputWordSwap  = 0x200000U,
+    kDCP_OutputByteSwap = 0x400000U,
+    kDCP_OutputWordSwap = 0x800000U,
+} dcp_swap_t;
+
+/*! @brief DCP's work packet. */
+typedef struct _dcp_work_packet
+{
+    uint32_t nextCmdAddress;
+    uint32_t control0;
+    uint32_t control1;
+    uint32_t sourceBufferAddress;
+    uint32_t destinationBufferAddress;
+    uint32_t bufferSize;
+    uint32_t payloadPointer;
+    uint32_t status;
+} dcp_work_packet_t;
+
+/*! @brief Specify DCP's key resource and DCP channel. */
+typedef struct _dcp_handle
+{
+    dcp_channel_t channel;  /*!< Specify DCP channel. */
+    dcp_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify DCP key slot. */
+    uint32_t swapConfig;    /*!< For configuration of key, input, output byte/word swap options */
+    uint32_t keyWord[4];
+    uint32_t iv[4];
+} dcp_handle_t;
+
+/*! @brief DCP's context buffer, used by DCP for context switching between channels. */
+typedef struct _dcp_context
+{
+    uint32_t x[208 / sizeof(uint32_t)];
+} dcp_context_t;
+
+/*! @brief DCP's configuration structure. */
+typedef struct _dcp_config
+{
+    bool gatherResidualWrites;      /*!< Enable the ragged writes to the unaligned buffers. */
+    bool enableContextCaching;      /*!< Enable the caching of contexts between the operations. */
+    bool enableContextSwitching;    /*!< Enable automatic context switching for the channels. */
+    uint8_t enableChannel;          /*!< DCP channel enable. */
+    uint8_t enableChannelInterrupt; /*!< Per-channel interrupt enable. */
+} dcp_config_t;
+
+/*! @} */
+
+#ifndef DCP_USE_DCACHE
+#define DCP_USE_DCACHE 1
+#endif
+/* 1 - driver supports DCACHE, 0 - drivers does not support DCACHE */
+/* When enable (DCP_USE_DCACHE = 1) Input/output buffers and hash ctx should be in */
+/* non-cached memory or handled properly (Clean & Invalidate DCACHE) */
+
+/*******************************************************************************
+ * AES Definitions
+ *******************************************************************************/
+
+/*!
+ * @addtogroup dcp_driver_aes
+ * @{
+ */
+
+/*! AES block size in bytes */
+#define DCP_AES_BLOCK_SIZE 16
+
+/*!
+ *@}
+ */ /* end of dcp_driver_aes */
+
+/*******************************************************************************
+ * HASH Definitions
+ ******************************************************************************/
+/*!
+ * @addtogroup dcp_driver_hash
+ * @{
+ */
+
+/* DCP cannot correctly compute hash for message with zero size. When enabled, driver bypases DCP and returns correct
+ * hash value. If you are sure, that the driver will never be called with zero sized message, you can disable this
+ * feature to reduce code size */
+#define DCP_HASH_CAVP_COMPATIBLE
+
+/*! @brief Supported cryptographic block cipher functions for HASH creation */
+typedef enum _dcp_hash_algo_t
+{
+    kDCP_Sha1,   /*!< SHA_1 */
+    kDCP_Sha256, /*!< SHA_256 */
+    kDCP_Crc32,  /*!< CRC_32 */
+} dcp_hash_algo_t;
+
+/*! @brief DCP HASH Context size. */
+#define DCP_SHA_BLOCK_SIZE  128U               /*!< internal buffer block size  */
+#define DCP_HASH_BLOCK_SIZE DCP_SHA_BLOCK_SIZE /*!< DCP hash block size  */
+
+/*! @brief DCP HASH Context size. */
+#define DCP_HASH_CTX_SIZE 64
+
+/*! @brief Storage type used to save hash context. */
+typedef struct _dcp_hash_ctx_t
+{
+    uint32_t x[DCP_HASH_CTX_SIZE];
+} dcp_hash_ctx_t;
+
+/*!
+ *@}
+ */ /* end of dcp_driver_hash */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup dcp_driver
+ * @{
+ */
+
+/*!
+ * @brief   Enables clock to and enables DCP
+ *
+ * Enable DCP clock and configure DCP.
+ *
+ * @param base DCP base address
+ * @param config Pointer to configuration structure.
+ */
+void DCP_Init(DCP_Type *base, const dcp_config_t *config);
+
+/*!
+ * @brief   Disable DCP clock
+ *
+ * Reset DCP and Disable DCP clock.
+ *
+ * @param base DCP base address
+ */
+void DCP_Deinit(DCP_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the DCP configuration structure to a default value. The default
+ * values are as follows.
+ *   dcpConfig->gatherResidualWrites = true;
+ *   dcpConfig->enableContextCaching = true;
+ *   dcpConfig->enableContextSwitching = true;
+ *   dcpConfig->enableChannnel = kDCP_chEnableAll;
+ *   dcpConfig->enableChannelInterrupt = kDCP_chIntDisable;
+ *
+ * @param[out] config Pointer to configuration structure.
+ */
+void DCP_GetDefaultConfig(dcp_config_t *config);
+
+/*!
+ * @brief Poll and wait on DCP channel.
+ *
+ * Polls the specified DCP channel until current it completes activity.
+ *
+ * @param   base DCP peripheral base address.
+ * @param   handle Specifies DCP channel.
+ * @return  kStatus_Success When data processing completes without error.
+ * @return  kStatus_Fail When error occurs.
+ */
+status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle);
+
+/*!
+ *@}
+ */ /* end of dcp_driver */
+
+/*******************************************************************************
+ * AES API
+ ******************************************************************************/
+
+/*!
+ * @addtogroup dcp_driver_aes
+ * @{
+ */
+
+/*!
+ * @brief Set AES key to dcp_handle_t struct and optionally to DCP.
+ *
+ * Sets the AES key for encryption/decryption with the dcp_handle_t structure.
+ * The dcp_handle_t input argument specifies keySlot.
+ * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use
+ * status.
+ * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct.
+ * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2,
+ * kDCP_KeySlot3),
+ * this function will also load the supplied key to the specified keySlot in DCP.
+ *
+ * @param   base DCP peripheral base address.
+ * @param   handle Handle used for the request.
+ * @param   key 0-mod-4 aligned pointer to AES key.
+ * @param   keySize AES key size in bytes. Shall equal 16.
+ * @return  status from set key operation
+ */
+status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize);
+
+/*!
+ * @brief Encrypts AES on one or multiple 128-bit block(s).
+ *
+ * Encrypts AES.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from encrypt operation
+ */
+status_t DCP_AES_EncryptEcb(
+    DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size);
+
+/*!
+ * @brief Decrypts AES on one or multiple 128-bit block(s).
+ *
+ * Decrypts AES.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request.
+ * @param ciphertext Input plain text to encrypt
+ * @param[out] plaintext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from decrypt operation
+ */
+status_t DCP_AES_DecryptEcb(
+    DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size);
+
+/*!
+ * @brief Encrypts AES using CBC block mode.
+ *
+ * Encrypts AES using CBC block mode.
+ * The source plaintext and destination ciphertext can overlap in system memory.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+status_t DCP_AES_EncryptCbc(DCP_Type *base,
+                            dcp_handle_t *handle,
+                            const uint8_t *plaintext,
+                            uint8_t *ciphertext,
+                            size_t size,
+                            const uint8_t iv[16]);
+
+/*!
+ * @brief Decrypts AES using CBC block mode.
+ *
+ * Decrypts AES using CBC block mode.
+ * The source ciphertext and destination plaintext can overlap in system memory.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from decrypt operation
+ */
+status_t DCP_AES_DecryptCbc(DCP_Type *base,
+                            dcp_handle_t *handle,
+                            const uint8_t *ciphertext,
+                            uint8_t *plaintext,
+                            size_t size,
+                            const uint8_t iv[16]);
+
+/*!
+ *@}
+ */ /* end of dcp_driver_aes */
+
+/*!
+ * @addtogroup dcp_nonblocking_driver_aes
+ * @{
+ */
+/*!
+ * @brief Encrypts AES using the ECB block mode.
+ *
+ * Puts AES ECB encrypt work packet to DCP channel.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request.
+ * @param[out] dcpPacket Memory for the DCP work packet.
+ * @param plaintext Input plain text to encrypt.
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return kStatus_Success The work packet has been scheduled at DCP channel.
+ * @return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *plaintext,
+                                       uint8_t *ciphertext,
+                                       size_t size);
+
+/*!
+ * @brief Decrypts AES using ECB block mode.
+ *
+ * Puts AES ECB decrypt dcpPacket to DCP input job ring.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request.
+ * @param[out] dcpPacket Memory for the DCP work packet.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return kStatus_Success The work packet has been scheduled at DCP channel.
+ * @return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *ciphertext,
+                                       uint8_t *plaintext,
+                                       size_t size);
+
+/*!
+ * @brief Encrypts AES using CBC block mode.
+ *
+ * Puts AES CBC encrypt dcpPacket to DCP input job ring.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request. Specifies jobRing.
+ * @param[out] dcpPacket Memory for the DCP work packet.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return kStatus_Success The work packet has been scheduled at DCP channel.
+ * @return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *plaintext,
+                                       uint8_t *ciphertext,
+                                       size_t size,
+                                       const uint8_t *iv);
+
+/*!
+ * @brief Decrypts AES using CBC block mode.
+ *
+ * Puts AES CBC decrypt dcpPacket to DCP input job ring.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for this request. Specifies jobRing.
+ * @param[out] dcpPacket Memory for the DCP work packet.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return kStatus_Success The work packet has been scheduled at DCP channel.
+ * @return kStatus_DCP_Again The DCP channel is busy processing previous request.
+ */
+status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base,
+                                       dcp_handle_t *handle,
+                                       dcp_work_packet_t *dcpPacket,
+                                       const uint8_t *ciphertext,
+                                       uint8_t *plaintext,
+                                       size_t size,
+                                       const uint8_t *iv);
+
+/*!
+ *@}
+ */ /* end of dcp_nonblocking_driver_aes */
+
+/*******************************************************************************
+ * HASH API
+ ******************************************************************************/
+
+/*!
+ * @addtogroup dcp_driver_hash
+ * @{
+ */
+/*!
+ * @brief Initialize HASH context
+ *
+ * This function initializes the HASH.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Specifies the DCP channel used for hashing.
+ * @param[out] ctx Output hash context
+ * @param algo Underlaying algorithm to use for hash computation.
+ * @return Status of initialization
+ */
+status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo);
+
+/*!
+ * @brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed. The functions blocks. If it returns kStatus_Success, the running hash
+ * has been updated (DCP has processed the input data), so the memory at the input pointer
+ * can be released back to system. The DCP context buffer is updated with the running hash
+ * and with all necessary information to support possible context switch.
+ *
+ * @param base DCP peripheral base address
+ * @param[in,out] ctx HASH context
+ * @param input Input data
+ * @param inputSize Size of input data in bytes
+ * @return Status of the hash update operation
+ */
+status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize);
+
+/*!
+ * @brief Finalize hashing
+ *
+ * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context.
+ *
+ * @param base DCP peripheral base address
+ * @param[in,out] ctx Input hash context
+ * @param[out] output Output hash data
+ * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
+ * output[] buffer. On function return, it stores the number of updated output bytes.
+ * @return Status of the hash finish operation
+ */
+status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize);
+
+/*!
+ * @brief Create HASH on given data
+ *
+ * Perform the full SHA or CRC32 in one function call. The function is blocking.
+ *
+ * @param base DCP peripheral base address
+ * @param handle Handle used for the request.
+ * @param algo Underlaying algorithm to use for hash computation.
+ * @param input Input data
+ * @param inputSize Size of input data in bytes
+ * @param[out] output Output hash data
+ * @param[out] outputSize Output parameter storing the size of the output hash in bytes
+ * @return Status of the one call hash operation.
+ */
+status_t DCP_HASH(DCP_Type *base,
+                  dcp_handle_t *handle,
+                  dcp_hash_algo_t algo,
+                  const uint8_t *input,
+                  size_t inputSize,
+                  uint8_t *output,
+                  size_t *outputSize);
+
+/*!
+ *@}
+ */ /* end of dcp_driver_hash */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_DCP_H_ */
diff --git a/nxp/source/nxp.c b/nxp/source/nxp.c
index a3e1f0c..fe33bd3 100644
--- a/nxp/source/nxp.c
+++ b/nxp/source/nxp.c
@@ -40,6 +40,7 @@
 #include "fsl_csi.h"
 #include "MIMXRT1064.h"
 #include "fsl_debug_console.h"
+#include "fsl_trng.h"
 #include "hal.h"
 
 struct gpio_pin_spec {
@@ -66,6 +67,10 @@ hal_err_t hal_init(void) {
 
   BOARD_InitCameraResource();
 
+  trng_config_t trngConfig;
+  TRNG_GetDefaultConfig(&trngConfig);
+  TRNG_Init(TRNG, &trngConfig);
+
   return HAL_OK;
 }
 
@@ -80,4 +85,8 @@ hal_err_t hal_gpio_set(hal_gpio_pin_t pin, hal_gpio_state_t state) {
   return HAL_OK;
 }
 
+void random_buffer(uint8_t *buf, size_t len) {
+  TRNG_GetRandomData(TRNG, buf, len);
+}
+