189 lines
9.6 KiB
Plaintext
189 lines
9.6 KiB
Plaintext
// Copyright (c) 2014-2016 Khronos Group. This work is licensed under a
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// Creative Commons Attribution 4.0 International License; see
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// http://creativecommons.org/licenses/by/4.0/
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VkMemoryBarrier(3)
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==================
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Name
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----
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VkMemoryBarrier - Structure specifying a memory barrier
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C Specification
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---------------
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// refBegin VkMemoryBarrier - Structure specifying a memory barrier
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The sname:VkMemoryBarrier structure is defined as:
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include::../api/structs/VkMemoryBarrier.txt[]
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Members
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-------
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* pname:sType is the type of this structure.
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* pname:pNext is `NULL` or a pointer to an extension-specific structure.
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* pname:srcAccessMask is a bitmask of the classes of memory accesses
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performed by the first set of commands that will participate in
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the dependency.
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* pname:dstAccessMask is a bitmask of the classes of memory accesses
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performed by the second set of commands that will participate in
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the dependency.
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Description
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-----------
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pname:srcAccessMask and pname:dstAccessMask, along with pname:srcStageMask
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and pname:dstStageMask from flink:vkCmdPipelineBarrier, define the two
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halves of a memory dependency and an execution dependency. Memory accesses
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using the set of access types in pname:srcAccessMask performed in pipeline
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stages in pname:srcStageMask by the first set of commands must: complete and
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be available to later commands. The side effects of the first set of
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commands will be visible to memory accesses using the set of access types in
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pname:dstAccessMask performed in pipeline stages in pname:dstStageMask by
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the second set of commands. If the barrier is by-region, these requirements
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only apply to invocations within the same framebuffer-space region, for
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pipeline stages that perform framebuffer-space work. The execution
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dependency guarantees that execution of work by the destination stages of
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the second set of commands will not begin until execution of work by the
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source stages of the first set of commands has completed.
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A common type of memory dependency is to avoid a read-after-write hazard. In
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this case, the source access mask and stages will include writes from a
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particular stage, and the destination access mask and stages will indicate
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how those writes will be read in subsequent commands. However, barriers can:
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also express write-after-read dependencies and write-after-write
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dependencies, and are even useful to express read-after-read dependencies
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across an image layout change.
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// refBegin VkAccessFlagBits - Bitmask specifying classes of memory access the will participate in a memory barrier dependency
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Bits which can: be set in slink:VkMemoryBarrier::pname:srcAccessMask and
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slink:VkMemoryBarrier::pname:dstAccessMask include:
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[[synchronization-access-flags]]
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include::../api/enums/VkAccessFlagBits.txt[]
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* ename:VK_ACCESS_INDIRECT_COMMAND_READ_BIT indicates that the access is
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an indirect command structure read as part of an indirect drawing
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command.
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* ename:VK_ACCESS_INDEX_READ_BIT indicates that the access is an index
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buffer read.
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* ename:VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT indicates that the access is a
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read via the vertex input bindings.
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* ename:VK_ACCESS_UNIFORM_READ_BIT indicates that the access is a read via
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a uniform buffer or dynamic uniform buffer descriptor.
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* ename:VK_ACCESS_INPUT_ATTACHMENT_READ_BIT indicates that the access is a
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read via an input attachment descriptor.
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* ename:VK_ACCESS_SHADER_READ_BIT indicates that the access is a read from
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a shader via any other descriptor type.
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* ename:VK_ACCESS_SHADER_WRITE_BIT indicates that the access is a write
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or atomic from a shader via the same descriptor types as in
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ename:VK_ACCESS_SHADER_READ_BIT.
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* ename:VK_ACCESS_COLOR_ATTACHMENT_READ_BIT indicates that the access is a
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read via a color attachment.
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* ename:VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT indicates that the access is
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a write via a color or resolve attachment.
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* ename:VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT indicates that the
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access is a read via a depth/stencil attachment.
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* ename:VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT indicates that the
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access is a write via a depth/stencil attachment.
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* ename:VK_ACCESS_TRANSFER_READ_BIT indicates that the access is a read
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from a transfer (copy, blit, resolve, etc.) operation. For the complete
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set of transfer operations, see
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<<synchronization-transfer,ename:VK_PIPELINE_STAGE_TRANSFER_BIT>>.
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* ename:VK_ACCESS_TRANSFER_WRITE_BIT indicates that the access is a write
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from a transfer (copy, blit, resolve, etc.) operation. For the complete
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set of transfer operations, see
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<<synchronization-transfer,ename:VK_PIPELINE_STAGE_TRANSFER_BIT>>.
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* ename:VK_ACCESS_HOST_READ_BIT indicates that the access is a read via
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the host.
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* ename:VK_ACCESS_HOST_WRITE_BIT indicates that the access is a write via
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the host.
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* ename:VK_ACCESS_MEMORY_READ_BIT indicates that the access is a read via
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a non-specific unit attached to the memory. This unit may: be external
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to the Vulkan device or otherwise not part of the core Vulkan pipeline.
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When included in pname:dstAccessMask, all writes using access types in
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pname:srcAccessMask performed by pipeline stages in pname:srcStageMask
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must: be visible in memory.
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* ename:VK_ACCESS_MEMORY_WRITE_BIT indicates that the access is a write
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via a non-specific unit attached to the memory. This unit may: be
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external to the Vulkan device or otherwise not part of the core Vulkan
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pipeline. When included in pname:srcAccessMask, all access types in
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pname:dstAccessMask from pipeline stages in pname:dstStageMask will
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observe the side effects of commands that executed before the barrier.
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When included in pname:dstAccessMask all writes using access types in
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pname:srcAccessMask performed by pipeline stages in pname:srcStageMask
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must: be visible in memory.
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Color attachment reads and writes are automatically (without memory or
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execution dependencies) coherent and ordered against themselves and each
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other for a given sample within a subpass of a render pass instance,
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executing in <<fundamentals-queueoperation-apiorder,API order>>. Similarly,
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depth/stencil attachment reads and writes are automatically coherent and
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ordered against themselves and each other in the same circumstances.
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Shader reads and/or writes through two variables (in the same or different
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shader invocations) decorated with code:Coherent and which use the same
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image view or buffer view are automatically coherent with each other, but
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require execution dependencies if a specific order is desired. Similarly,
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shader atomic operations are coherent with each other and with code:Coherent
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variables. Non-code:Coherent shader memory accesses require memory
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dependencies for writes to be available and reads to be visible.
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Certain memory access types are only supported on queues that support a
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particular set of operations. The following table lists, for each access
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flag, which queue capability flag must: be supported by the queue. When
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multiple flags are enumerated in the second column of the table it means
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that the access type is supported on the queue if it supports any of the
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listed capability flags. For further details on queue capabilities see
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<<devsandqueues-physical-device-enumeration,Physical Device Enumeration>>
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and <<devsandqueues-queues,Queues>>.
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.Supported access flags
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[width="100%",cols="67%,33%",options="header",align="center"]
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|========================================
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|Access flag | Required queue capability flag
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|ename:VK_ACCESS_INDIRECT_COMMAND_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
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|ename:VK_ACCESS_INDEX_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT
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|ename:VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT
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|ename:VK_ACCESS_UNIFORM_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
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|ename:VK_ACCESS_INPUT_ATTACHMENT_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT
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|ename:VK_ACCESS_SHADER_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
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|ename:VK_ACCESS_SHADER_WRITE_BIT | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
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|ename:VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT
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|ename:VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | ename:VK_QUEUE_GRAPHICS_BIT
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|ename:VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT
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|ename:VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT | ename:VK_QUEUE_GRAPHICS_BIT
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|ename:VK_ACCESS_TRANSFER_READ_BIT | ename:VK_QUEUE_GRAPHICS_BIT, ename:VK_QUEUE_COMPUTE_BIT or ename:VK_QUEUE_TRANSFER_BIT
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|ename:VK_ACCESS_TRANSFER_WRITE_BIT | ename:VK_QUEUE_GRAPHICS_BIT, ename:VK_QUEUE_COMPUTE_BIT or ename:VK_QUEUE_TRANSFER_BIT
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|ename:VK_ACCESS_HOST_READ_BIT | None
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|ename:VK_ACCESS_HOST_WRITE_BIT | None
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|ename:VK_ACCESS_MEMORY_READ_BIT | None
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|ename:VK_ACCESS_MEMORY_WRITE_BIT | None
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|========================================
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include::../validity/structs/VkMemoryBarrier.txt[]
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See Also
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--------
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elink:VkAccessFlags, elink:VkStructureType, flink:vkCmdPipelineBarrier, flink:vkCmdWaitEvents
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Document Notes
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--------------
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For more information, see the Vulkan Specification at URL
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https://www.khronos.org/registry/vulkan/specs/1.0/xhtml/vkspec.html#VkMemoryBarrier
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This page is extracted from the Vulkan Specification.
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Fixes and changes should be made to the Specification,not directly.
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include::footer.txt[]
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