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Reorder stage and access flags to match their definition order

This commit is contained in:
Petr Kraus 2018-07-12 17:42:56 +02:00
parent 831e2d4525
commit a67969af1f
1 changed files with 33 additions and 31 deletions
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64
chapters/synchronization.txt
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@ -293,16 +293,6 @@ include::../api/enums/VkPipelineStageFlagBits.txt[]
* ename:VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT specifies the stage of the
pipeline where any commands are initially received by the queue.
ifdef::VK_NVX_device_generated_commands[]
* ename:VK_PIPELINE_STAGE_COMMAND_PROCESS_BIT_NVX specifies the stage of
the pipeline where device-side generation of commands via
flink:vkCmdProcessCommandsNVX is handled.
endif::VK_NVX_device_generated_commands[]
ifdef::VK_EXT_conditional_rendering[]
* ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT specifies the
stage of the pipeline where the predicate of conditional rendering is
consumed.
endif::VK_EXT_conditional_rendering[]
* ename:VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT specifies the stage of the
pipeline where Draw/DispatchIndirect data structures are consumed.
ifdef::VK_NVX_device_generated_commands[]
@ -337,14 +327,14 @@ endif::VK_NVX_device_generated_commands[]
This stage also includes <<renderpass-load-store-ops, subpass load and
store operations>> and multisample resolve operations for framebuffer
attachments with a color format.
* ename:VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT specifies the execution of a
compute shader.
* [[synchronization-pipeline-stages-transfer]]
ename:VK_PIPELINE_STAGE_TRANSFER_BIT specifies the execution of copy
commands.
This includes the operations resulting from all <<copies,copy
commands>>, <<clears,clear commands>> (with the exception of
flink:vkCmdClearAttachments), and flink:vkCmdCopyQueryPoolResults.
* ename:VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT specifies the execution of a
compute shader.
* ename:VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT specifies the final stage in
the pipeline where operations generated by all commands complete
execution.
@ -354,9 +344,6 @@ endif::VK_NVX_device_generated_commands[]
* ename:VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT specifies the execution of all
graphics pipeline stages, and is equivalent to the logical OR of:
** ename:VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
ifdef::VK_EXT_conditional_rendering[]
** ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT
endif::VK_EXT_conditional_rendering[]
** ename:VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
** ename:VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
** ename:VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
@ -368,9 +355,22 @@ endif::VK_EXT_conditional_rendering[]
** ename:VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
** ename:VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
** ename:VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
ifdef::VK_EXT_conditional_rendering[]
** ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT
endif::VK_EXT_conditional_rendering[]
* ename:VK_PIPELINE_STAGE_ALL_COMMANDS_BIT is equivalent to the logical OR
of every other pipeline stage flag that is supported on the queue it is
used with.
ifdef::VK_EXT_conditional_rendering[]
* ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT specifies the
stage of the pipeline where the predicate of conditional rendering is
consumed.
endif::VK_EXT_conditional_rendering[]
ifdef::VK_NVX_device_generated_commands[]
* ename:VK_PIPELINE_STAGE_COMMAND_PROCESS_BIT_NVX specifies the stage of
the pipeline where device-side generation of commands via
flink:vkCmdProcessCommandsNVX is handled.
endif::VK_NVX_device_generated_commands[]
[NOTE]
.Note
@ -451,9 +451,6 @@ and <<devsandqueues-queues,Queues>>.
|====
|Pipeline stage flag | Required queue capability flag
|ename:VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT | None required
ifdef::VK_EXT_conditional_rendering[]
|ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
endif::VK_EXT_conditional_rendering[]
|ename:VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
|ename:VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | ename:VK_QUEUE_GRAPHICS_BIT
|ename:VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | ename:VK_QUEUE_GRAPHICS_BIT
@ -470,6 +467,9 @@ endif::VK_EXT_conditional_rendering[]
|ename:VK_PIPELINE_STAGE_HOST_BIT | None required
|ename:VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | ename:VK_QUEUE_GRAPHICS_BIT
|ename:VK_PIPELINE_STAGE_ALL_COMMANDS_BIT | None required
ifdef::VK_EXT_conditional_rendering[]
|ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
endif::VK_EXT_conditional_rendering[]
ifdef::VK_NVX_device_generated_commands[]
|ename:VK_PIPELINE_STAGE_COMMAND_PROCESS_BIT_NVX | ename:VK_QUEUE_GRAPHICS_BIT or ename:VK_QUEUE_COMPUTE_BIT
endif::VK_NVX_device_generated_commands[]
@ -592,10 +592,6 @@ Access types that can: be set in an access mask include:
include::../api/enums/VkAccessFlagBits.txt[]
ifdef::VK_EXT_conditional_rendering[]
* ename:VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT specifies read access
to a predicate as part of conditional rendering.
endif::VK_EXT_conditional_rendering[]
* ename:VK_ACCESS_INDIRECT_COMMAND_READ_BIT specifies read access to an
indirect command structure read as part of an indirect drawing or
dispatch command.
@ -627,9 +623,6 @@ endif::VK_EXT_conditional_rendering[]
ifdef::VK_EXT_blend_operation_advanced[]
It does not include <<framebuffer-blend-advanced,advanced blend
operations>>.
* ename:VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT is similar to
ename:VK_ACCESS_COLOR_ATTACHMENT_READ_BIT, but also includes
<<framebuffer-blend-advanced,advanced blend operations>>.
endif::VK_EXT_blend_operation_advanced[]
* ename:VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT specifies write access to a
<<renderpass, color or resolve attachment>> during a <<renderpass,
@ -672,12 +665,21 @@ endif::VK_EXT_blend_operation_advanced[]
When included in a destination access mask, makes all available writes
visible to all future write accesses on entities known to the Vulkan
device.
ifdef::VK_EXT_conditional_rendering[]
* ename:VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT specifies read access
to a predicate as part of conditional rendering.
endif::VK_EXT_conditional_rendering[]
ifdef::VK_NVX_device_generated_commands[]
* ename:VK_ACCESS_COMMAND_PROCESS_READ_BIT_NVX specifies reads from
sname:VkBuffer inputs to flink:vkCmdProcessCommandsNVX.
* ename:VK_ACCESS_COMMAND_PROCESS_WRITE_BIT_NVX specifies writes to the
target command buffer in flink:vkCmdProcessCommandsNVX.
endif::VK_NVX_device_generated_commands[]
ifdef::VK_EXT_blend_operation_advanced[]
* ename:VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT is similar to
ename:VK_ACCESS_COLOR_ATTACHMENT_READ_BIT, but also includes
<<framebuffer-blend-advanced,advanced blend operations>>.
endif::VK_EXT_blend_operation_advanced[]
Certain access types are only performed by a subset of pipeline stages.
Any synchronization command that takes both stage masks and access masks
@ -695,9 +697,6 @@ perform that type of access.
[cols="50,50",options="header"]
|====
|Access flag | Supported pipeline stages
ifdef::VK_EXT_conditional_rendering[]
|ename:VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT | ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT
endif::VK_EXT_conditional_rendering[]
|ename:VK_ACCESS_INDIRECT_COMMAND_READ_BIT | ename:VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|ename:VK_ACCESS_INDEX_READ_BIT | ename:VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|ename:VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | ename:VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
@ -706,9 +705,6 @@ endif::VK_EXT_conditional_rendering[]
|ename:VK_ACCESS_SHADER_READ_BIT | ename:VK_PIPELINE_STAGE_VERTEX_SHADER_BIT, ename:VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT, ename:VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT, ename:VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT, ename:VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT, or ename:VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|ename:VK_ACCESS_SHADER_WRITE_BIT | ename:VK_PIPELINE_STAGE_VERTEX_SHADER_BIT, ename:VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT, ename:VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT, ename:VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT, ename:VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT, or ename:VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|ename:VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | ename:VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
ifdef::VK_EXT_blend_operation_advanced[]
|ename:VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT | ename:VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
endif::VK_EXT_blend_operation_advanced[]
|ename:VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | ename:VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|ename:VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | ename:VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT, or ename:VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|ename:VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT | ename:VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT, or ename:VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
@ -718,10 +714,16 @@ endif::VK_EXT_blend_operation_advanced[]
|ename:VK_ACCESS_HOST_WRITE_BIT | ename:VK_PIPELINE_STAGE_HOST_BIT
|ename:VK_ACCESS_MEMORY_READ_BIT | N/A
|ename:VK_ACCESS_MEMORY_WRITE_BIT | N/A
ifdef::VK_EXT_blend_operation_advanced[]
|ename:VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT | ename:VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
endif::VK_EXT_blend_operation_advanced[]
ifdef::VK_NVX_device_generated_commands[]
|ename:VK_ACCESS_COMMAND_PROCESS_READ_BIT_NVX | ename:VK_PIPELINE_STAGE_COMMAND_PROCESS_BIT_NVX
|ename:VK_ACCESS_COMMAND_PROCESS_WRITE_BIT_NVX | ename:VK_PIPELINE_STAGE_COMMAND_PROCESS_BIT_NVX
endif::VK_NVX_device_generated_commands[]
ifdef::VK_EXT_conditional_rendering[]
|ename:VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT | ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT
endif::VK_EXT_conditional_rendering[]
|====
[[synchronization-host-access-types]]