Fix ifdef inside VU entry in VkSubpassDependency
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@ -1099,23 +1099,9 @@ layouts as follows:
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ename:VK_SUBPASS_EXTERNAL
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* [[VUID-VkSubpassDependency-srcSubpass-00866]]
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If pname:srcSubpass is equal to pname:dstSubpass, pname:srcStageMask and
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pname:dstStageMask must: only contain one of
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ename:VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
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ifdef::VK_EXT_conditional_rendering[]
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ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT,
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endif::VK_EXT_conditional_rendering[]
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ename:VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT,
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ename:VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
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ename:VK_PIPELINE_STAGE_VERTEX_SHADER_BIT,
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ename:VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT,
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ename:VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT,
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ename:VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT,
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ename:VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT,
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ename:VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT,
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ename:VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT,
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ename:VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT,
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ename:VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, or
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ename:VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
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pname:dstStageMask must: only contain
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ename:VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT, or one of the
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<<synchronization-pipeline-stages-types,graphics pipeline stages>>
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* [[VUID-VkSubpassDependency-srcSubpass-00867]]
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If pname:srcSubpass is equal to pname:dstSubpass and not all of the
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stages in pname:srcStageMask and pname:dstStageMask are
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@ -549,8 +549,9 @@ guaranteed:
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* ename:VK_PIPELINE_STAGE_HOST_BIT
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ifdef::VK_EXT_conditional_rendering[]
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For conditional rendering operations, the pipeline stage where predicate
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read happens has no particular order relative to other stages.
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The conditional rendering stage is formally part of both the graphics, and
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the compute pipeline. The pipeline stage where the predicate read happens
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has unspecified order relative to other stages of these pipelines:
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* ename:VK_PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT
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endif::VK_EXT_conditional_rendering[]
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