2 Commits
Author SHA1 Message Date
Alex Jbanca 8a6632b94e perf(LeftJoinModel): Add LRU cache for right model data access
The right model data access is expensive because we need to search the right model for a matching key on every `data` call. This commit adds a LRU cache to the `data` call, storing by default up to 1000 rows.

The cache mechanism uses a QCache for fast index lookup and a std::list to preserve the access order and to ensure a controlled cache removal.

+ fix compilation errors on ConcatModel and WritableProxyModel
2025-08-15 16:17:16 +03:00
Michał Cieślak 777b05cc98 initial commit 2025-06-13 16:25:14 +02:00