mirror of
https://github.com/logos-storage/plonky2.git
synced 2026-01-27 01:53:12 +00:00
ed3f0d546f
* Complete versions of rotate left and shift left. * Implement rotate/shift right. * cargo fmt * Fix documentation. * Reduce visibility of helper functions. * Address Jaqui's PR comments. * Disable fall-through check as the run test assumes no failure here. * Try to fix doctest failure.
186 lines
8.9 KiB
Rust
186 lines
8.9 KiB
Rust
//! Arithmetic and logic unit.
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pub(crate) const IS_ADD: usize = super::START_ALU;
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pub(crate) const IS_SUB: usize = IS_ADD + 1;
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pub(crate) const IS_MUL_ADD: usize = IS_SUB + 1;
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pub(crate) const IS_DIV: usize = IS_MUL_ADD + 1;
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pub(crate) const IS_AND: usize = IS_DIV + 1;
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pub(crate) const IS_IOR: usize = IS_AND + 1;
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pub(crate) const IS_XOR: usize = IS_IOR + 1;
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pub(crate) const IS_ANDNOT: usize = IS_XOR + 1;
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pub(crate) const IS_NOT: usize = IS_ANDNOT + 1;
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pub(crate) const IS_ROTATE_LEFT: usize = IS_NOT + 1;
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pub(crate) const IS_ROTATE_RIGHT: usize = IS_ROTATE_LEFT + 1;
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pub(crate) const IS_SHIFT_LEFT: usize = IS_ROTATE_RIGHT + 1;
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pub(crate) const IS_SHIFT_RIGHT: usize = IS_SHIFT_LEFT + 1;
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pub(crate) const IS_ARITH_SHIFT_RIGHT: usize = IS_SHIFT_RIGHT + 1;
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pub(crate) const ALL_OPERATIONS: [usize; 14] = [
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IS_ADD,
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IS_SUB,
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IS_MUL_ADD,
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IS_DIV,
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IS_AND,
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IS_IOR,
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IS_XOR,
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IS_ANDNOT,
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IS_NOT,
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IS_ROTATE_LEFT,
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IS_ROTATE_RIGHT,
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IS_SHIFT_LEFT,
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IS_SHIFT_RIGHT,
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IS_ARITH_SHIFT_RIGHT,
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];
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const START_SHARED_COLS: usize = IS_ARITH_SHIFT_RIGHT + 1;
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/// Within the ALU, there are shared columns which can be used by any arithmetic/logic
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/// circuit, depending on which one is active this cycle.
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// Can be increased as needed as other operations are implemented.
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const NUM_SHARED_COLS: usize = 130;
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const fn shared_col(i: usize) -> usize {
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debug_assert!(i < NUM_SHARED_COLS);
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START_SHARED_COLS + i
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}
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/// The first value to be added; treated as an unsigned u32.
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pub(crate) const COL_ADD_INPUT_0: usize = shared_col(0);
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/// The second value to be added; treated as an unsigned u32.
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pub(crate) const COL_ADD_INPUT_1: usize = shared_col(1);
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/// The third value to be added; treated as an unsigned u32.
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pub(crate) const COL_ADD_INPUT_2: usize = shared_col(2);
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// Note: Addition outputs three 16-bit chunks, and since these values need to be range-checked
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// anyway, we might as well use the range check unit's columns as our addition outputs. So the
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// three proceeding columns are basically aliases, not columns owned by the ALU.
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/// The first 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_ADD_OUTPUT_0: usize = super::range_check_16::col_rc_16_input(0);
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/// The second 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_ADD_OUTPUT_1: usize = super::range_check_16::col_rc_16_input(1);
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/// The third 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_ADD_OUTPUT_2: usize = super::range_check_16::col_rc_16_input(2);
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/// Inputs for subtraction; the second value is subtracted from the
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/// first; inputs treated as an unsigned u32.
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pub(crate) const COL_SUB_INPUT_0: usize = shared_col(0);
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pub(crate) const COL_SUB_INPUT_1: usize = shared_col(1);
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/// The first 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_SUB_OUTPUT_0: usize = super::range_check_16::col_rc_16_input(0);
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/// The second 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_SUB_OUTPUT_1: usize = super::range_check_16::col_rc_16_input(1);
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/// The borrow output
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pub(crate) const COL_SUB_OUTPUT_BORROW: usize = super::boolean::col_bit(0);
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/// The first value to be multiplied; treated as an unsigned u32.
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pub(crate) const COL_MUL_ADD_FACTOR_0: usize = shared_col(0);
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/// The second value to be multiplied; treated as an unsigned u32.
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pub(crate) const COL_MUL_ADD_FACTOR_1: usize = shared_col(1);
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/// The value to be added to the product; treated as an unsigned u32.
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pub(crate) const COL_MUL_ADD_ADDEND: usize = shared_col(2);
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/// The inverse of `u32::MAX - result_hi`, where `output_hi` is the high 32-bits of the result.
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/// See https://hackmd.io/NC-yRmmtRQSvToTHb96e8Q#Checking-element-validity
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pub(crate) const COL_MUL_ADD_RESULT_CANONICAL_INV: usize = shared_col(3);
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/// The first 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_MUL_ADD_OUTPUT_0: usize = super::range_check_16::col_rc_16_input(0);
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/// The second 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_MUL_ADD_OUTPUT_1: usize = super::range_check_16::col_rc_16_input(1);
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/// The third 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_MUL_ADD_OUTPUT_2: usize = super::range_check_16::col_rc_16_input(2);
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/// The fourth 16-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_MUL_ADD_OUTPUT_3: usize = super::range_check_16::col_rc_16_input(3);
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/// Dividend for division, as an unsigned u32
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pub(crate) const COL_DIV_INPUT_DIVIDEND: usize = shared_col(0);
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/// Divisor for division, as an unsigned u32
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pub(crate) const COL_DIV_INPUT_DIVISOR: usize = shared_col(1);
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/// Inverse of divisor, if one exists, and 0 otherwise
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pub(crate) const COL_DIV_INVDIVISOR: usize = shared_col(2);
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/// 1 if divisor is nonzero and 0 otherwise
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pub(crate) const COL_DIV_NONZERO_DIVISOR: usize = shared_col(3);
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/// The first 16-bit chunk of the quotient, based on little-endian ordering.
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pub(crate) const COL_DIV_OUTPUT_QUOT_0: usize = super::range_check_16::col_rc_16_input(0);
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/// The second 16-bit chunk of the quotient, based on little-endian ordering.
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pub(crate) const COL_DIV_OUTPUT_QUOT_1: usize = super::range_check_16::col_rc_16_input(1);
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/// The first 16-bit chunk of the remainder, based on little-endian ordering.
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pub(crate) const COL_DIV_OUTPUT_REM_0: usize = super::range_check_16::col_rc_16_input(2);
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/// The second 16-bit chunk of the remainder, based on little-endian ordering.
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pub(crate) const COL_DIV_OUTPUT_REM_1: usize = super::range_check_16::col_rc_16_input(3);
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/// The first 16-bit chunk of a temporary value (divisor - remainder - 1).
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pub(crate) const COL_DIV_RANGE_CHECKED_TMP_0: usize = super::range_check_16::col_rc_16_input(4);
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/// The second 16-bit chunk of a temporary value (divisor - remainder - 1).
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pub(crate) const COL_DIV_RANGE_CHECKED_TMP_1: usize = super::range_check_16::col_rc_16_input(5);
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///
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/// Bitwise logic operations
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///
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/// Bit decomposition of 64-bit values, as 32-bit low and high halves.
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const fn gen_bitop_nbit_input_regs<const N: usize>(start: usize) -> [usize; N] {
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let mut regs = [0usize; N];
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let mut i = 0;
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while i < N {
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regs[i] = shared_col(start + i);
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i += 1;
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}
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regs
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}
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pub(crate) const COL_BIT_DECOMP_INPUT_A_LO_BIN_REGS: [usize; 32] =
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gen_bitop_nbit_input_regs::<32>(0);
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pub(crate) const COL_BIT_DECOMP_INPUT_A_HI_BIN_REGS: [usize; 32] =
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gen_bitop_nbit_input_regs::<32>(32);
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pub(crate) const COL_BIT_DECOMP_INPUT_B_LO_BIN_REGS: [usize; 32] =
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gen_bitop_nbit_input_regs::<32>(64);
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pub(crate) const COL_BIT_DECOMP_INPUT_B_HI_BIN_REGS: [usize; 32] =
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gen_bitop_nbit_input_regs::<32>(96);
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/// The first 32-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_BITOP_OUTPUT_0: usize = shared_col(128);
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/// The second 32-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_BITOP_OUTPUT_1: usize = shared_col(129);
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/// Input value to be rotated or shifted, low 32 bits
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pub(crate) const COL_ROTATE_SHIFT_INPUT_LO: usize = shared_col(0);
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/// Input value to be rotated or shifted, high 32 bits
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pub(crate) const COL_ROTATE_SHIFT_INPUT_HI: usize = shared_col(1);
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/// Bit decomposition of EXP, which is DELTA mod 32 for left
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/// rotate/shift; bit decomposition of (32 - DELTA mod 32) mod 32 for
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/// right rotate/shift.
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pub(crate) const COL_ROTATE_SHIFT_EXP_BITS: [usize; 5] = gen_bitop_nbit_input_regs::<5>(2);
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/// Top bit of the 6-bit value DELTA; also interpreted as DELTA >= 32.
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pub(crate) const COL_ROTATE_SHIFT_DELTA_DIV32: usize = shared_col(7);
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/// POW_EXP = 2^EXP, the AUX_i vars are helpers.
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pub(crate) const COL_ROTATE_SHIFT_POW_EXP_AUX_0: usize = shared_col(8);
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pub(crate) const COL_ROTATE_SHIFT_POW_EXP_AUX_1: usize = shared_col(9);
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pub(crate) const COL_ROTATE_SHIFT_POW_EXP_AUX_2: usize = shared_col(10);
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pub(crate) const COL_ROTATE_SHIFT_POW_EXP: usize = shared_col(11);
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/// low 32 bits of INPUT_LO * 2^EXP
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pub(crate) const COL_ROTATE_SHIFT_INPUT_LO_DISPLACED_0: usize = shared_col(12);
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/// high 32 bits of INPUT_LO * 2^EXP
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pub(crate) const COL_ROTATE_SHIFT_INPUT_LO_DISPLACED_1: usize = shared_col(13);
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/// low 32 bits of INPUT_HI * 2^EXP
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pub(crate) const COL_ROTATE_SHIFT_INPUT_HI_DISPLACED_0: usize = shared_col(14);
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/// high 32 bits of INPUT_HI * 2^EXP
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pub(crate) const COL_ROTATE_SHIFT_INPUT_HI_DISPLACED_1: usize = shared_col(15);
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pub(crate) const COL_ROTATE_SHIFT_INPUT_LO_DISPLACED_AUX_0: usize = shared_col(16);
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pub(crate) const COL_ROTATE_SHIFT_INPUT_LO_DISPLACED_AUX_1: usize = shared_col(17);
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pub(crate) const COL_ROTATE_SHIFT_INPUT_HI_DISPLACED_AUX_0: usize = shared_col(18);
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pub(crate) const COL_ROTATE_SHIFT_INPUT_HI_DISPLACED_AUX_1: usize = shared_col(19);
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/// The first 32-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_ROTATE_SHIFT_OUTPUT_0: usize = shared_col(20);
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/// The second 32-bit chunk of the output, based on little-endian ordering.
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pub(crate) const COL_ROTATE_SHIFT_OUTPUT_1: usize = shared_col(21);
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pub(super) const END: usize = START_SHARED_COLS + NUM_SHARED_COLS;
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