8 Commits

Author SHA1 Message Date
Jacqueline Nabaglo
b98dd47820
Permission levels, jumps, traps (#653)
* Permission levels, jumps, traps

* Tests passing

* PR comments + documentation

* Docs + minor bugfixes

* Tests

* Use already-defined `stop` and `exception` (but renamed to `sys_stop`, `fault_exception`)

* Daniel comments
2022-08-16 09:46:10 -07:00
Daniel Lubarov
cc61c7211c Core transaction processing logic
With lots of TODOs to fill in afterward; this is just a start.
2022-08-12 17:20:18 -07:00
Jacqueline Nabaglo
24bb632358
Implement PANIC instruction (#644)
* Implement PANIC instruction

* Minor: comments
2022-07-29 12:04:42 -07:00
Jacqueline Nabaglo
16c2bee4b9
Increment program counter on native instructions (#641) 2022-07-28 17:30:20 -07:00
Daniel Lubarov
b2f09881c0 Merge branch 'main' into cpu_shared_cols 2022-07-28 13:41:46 -07:00
Daniel Lubarov
6ee2e4fcd8 move 2022-07-18 12:21:29 -07:00
Daniel Lubarov
49a785f2bd rename 2022-07-18 12:21:00 -07:00
Daniel Lubarov
3d83d63f0b Shared CPU columns
I was thinking we could have two sets of shared columns:
- First, a set of "core" columns which would contain instruction decoding registers during an execution cycle, or some counter data during a kernel bootloading cycle.
- Second, a set of "general" columns which would be more general-purpose. For now it could contain "looking" columns for most CTLs (Keccak, arithmetic and logic; NOT memory since memory can be used simultaneously with the others). It could potentially be reused for other things too, such as the registers used for `EQ` and `IS_ZERO` (but I know it's nontrivial to share those since we would need to use lower-degree constraints, so I wouldn't bother for now).

This PR implements just the latter. If it looks good I'll proceed with the former afterward.
2022-07-18 12:15:41 -07:00