21 Commits

Author SHA1 Message Date
Jacqueline Nabaglo
ec3391f9c4
Add Fp254 ops to the CPU table (#779)
* Add Fp254 ops to the CPU table

* Add forgotten file
2022-10-13 14:02:19 -07:00
Daniel Lubarov
9e483528d3 MPT hashing logic, part 3 2022-10-02 09:11:39 -07:00
Jacqueline Nabaglo
e978425b26
Connect stack to memory (#735)
* Connect stack to memory

* Daniel PR comment
2022-09-28 15:18:56 -07:00
Jacqueline Nabaglo
084700a7f4
Memory channel for program counter (#717) 2022-09-22 18:09:23 -07:00
Jacqueline Nabaglo
cae5f4870c
Stack pointer + underflow/overflow checks (#710)
* Stack pointer + underflow/overflow checks

* Daniel comments

* Extra docs
2022-09-10 13:20:30 -07:00
Daniel Lubarov
2c77247d43 Keccak sponge STARK
It contains a row for each absorb step of the sponge.
2022-09-01 09:41:19 -07:00
Jacqueline Nabaglo
4c52d37546
Save columns by verifying invalid opcodes in software (#701)
* Save columns by verifying invalid opcodes in software

* Autogenerate invalid opcode bitfield (Daniel comment)

* Remove unnecessary panic label
2022-08-30 13:06:03 -07:00
Jacqueline Nabaglo
013bf6471d
Transpose memory columns (make it an array of channel structs) (#700) 2022-08-26 22:05:16 -07:00
Jacqueline Nabaglo
f48de368a9
Make jumps, logic, and syscalls read from/write to memory columns (#699)
* Make jumps, logic, and syscalls read from/write to memory columns

* Change CTL convention (outputs precede inputs)

* Change convention so outputs follow inputs in memory channel order
2022-08-26 14:39:39 -07:00
Daniel Lubarov
9671c1e535
Merge pull request #669 from mir-protocol/keccak_memory
Keccak memory stark
2022-08-25 15:55:48 -07:00
Jacqueline Nabaglo
f1a5b7b2d1
Delete opcode column (#672) 2022-08-25 11:56:25 -05:00
Daniel Lubarov
522cac5e15 Keccak memory stark 2022-08-24 09:29:17 -07:00
Jacqueline Nabaglo
5922c58730
Change logic limb size to 32 bits (#674)
* Change logic limb size to 32 bits

* Remove unnecessary columns (thx Daniel!)
2022-08-17 21:19:27 -07:00
Jacqueline Nabaglo
b98dd47820
Permission levels, jumps, traps (#653)
* Permission levels, jumps, traps

* Tests passing

* PR comments + documentation

* Docs + minor bugfixes

* Tests

* Use already-defined `stop` and `exception` (but renamed to `sys_stop`, `fault_exception`)

* Daniel comments
2022-08-16 09:46:10 -07:00
Daniel Lubarov
cc61c7211c Core transaction processing logic
With lots of TODOs to fill in afterward; this is just a start.
2022-08-12 17:20:18 -07:00
Jacqueline Nabaglo
24bb632358
Implement PANIC instruction (#644)
* Implement PANIC instruction

* Minor: comments
2022-07-29 12:04:42 -07:00
Jacqueline Nabaglo
16c2bee4b9
Increment program counter on native instructions (#641) 2022-07-28 17:30:20 -07:00
Daniel Lubarov
b2f09881c0 Merge branch 'main' into cpu_shared_cols 2022-07-28 13:41:46 -07:00
Daniel Lubarov
6ee2e4fcd8 move 2022-07-18 12:21:29 -07:00
Daniel Lubarov
49a785f2bd rename 2022-07-18 12:21:00 -07:00
Daniel Lubarov
3d83d63f0b Shared CPU columns
I was thinking we could have two sets of shared columns:
- First, a set of "core" columns which would contain instruction decoding registers during an execution cycle, or some counter data during a kernel bootloading cycle.
- Second, a set of "general" columns which would be more general-purpose. For now it could contain "looking" columns for most CTLs (Keccak, arithmetic and logic; NOT memory since memory can be used simultaneously with the others). It could potentially be reused for other things too, such as the registers used for `EQ` and `IS_ZERO` (but I know it's nontrivial to share those since we would need to use lower-degree constraints, so I wouldn't bother for now).

This PR implements just the latter. If it looks good I'll proceed with the former afterward.
2022-07-18 12:15:41 -07:00