5 Commits

Author SHA1 Message Date
Robin Salen
8a5eed9d1c
Fix shift constraint (#1280) 2023-10-09 07:41:30 -04:00
Robin Salen
06bc73f7ea
Combine arithmetic flags on the CPU side (#1187)
* Combine FP254 flags

* Combine basic binary ops together and do CTL with opcode value

* Combine ternary ops together

* Combine MUL DIV and MOD

* Combine shift operations

* Combine byte with other binary ops

* Fix tests

* Clean leftover comment

* Update from latest main

* Put the 'is_simulated' flag inside the Operation enum

* Cleaner way to handle "simulated" operations SHL and SHR.

* Fix comments.

* Minor: suggestion for re-expressing `combined_ops`.

* Update comment

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Co-authored-by: Hamish Ivey-Law <hamish@ivey-law.name>
2023-09-14 10:36:48 -04:00
Robin Salen
5f4b15af7a
Connect SHL/SHR operations to the Arithmetic table (#1166)
* Add corresponding arithmetic operations to shift ones

* Include SHL/SHR in the arithmetic CTL

* Prevent overflow

* Expand documentation for ctl_data_ternops()
2023-08-09 23:17:06 +10:00
Daniel Lubarov
1303a83f7f Misc witness generation fixes 2022-12-03 21:09:57 -08:00
Hamish Ivey-Law
1c87fbb712
EVM shift left/right operations (#801)
* First parts of shift implementation.

* Disable range check errors.

* Tidy up ASM.

* Update comments; fix some .sum() expressions.

* First full draft of shift left/right.

* Missed a +1.

* Clippy.

* Address Jacqui's comments.

* Add comment.

* Fix missing filter.

* Address second round of comments from Jacqui.
2022-11-09 10:47:15 +11:00