* Change padding rule for CPU
* Disable memory channels for padding rows
* Apply some of Jacqueline's comments
* Update halt routine
* Add clarifying comment
* Redundant constraints and padding bug
* Revert "Remove is_bootstrap_kernel column"
This reverts commit 49d92cb8f1b0ae9de76872f76af4429699ff692f.
* Make halt_state implicit
* Move halting logic constraints to dedicated module
* Include new module
* Update some comments
* Combine mstore_general and mload_general into one flag
* Add comments and make stack constraints cleaner.
* Fix number of native instructions
* Ordering
* Cleanup
* Update calls to stack eval from latest main
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Co-authored-by: Robin Salen <salenrobin@gmail.com>
* Combine FP254 flags
* Combine basic binary ops together and do CTL with opcode value
* Combine ternary ops together
* Combine MUL DIV and MOD
* Combine shift operations
* Combine byte with other binary ops
* Fix tests
* Clean leftover comment
* Update from latest main
* Put the 'is_simulated' flag inside the Operation enum
* Cleaner way to handle "simulated" operations SHL and SHR.
* Fix comments.
* Minor: suggestion for re-expressing `combined_ops`.
* Update comment
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Co-authored-by: Hamish Ivey-Law <hamish@ivey-law.name>
* First parts of shift implementation.
* Disable range check errors.
* Tidy up ASM.
* Update comments; fix some .sum() expressions.
* First full draft of shift left/right.
* Missed a +1.
* Clippy.
* Address Jacqui's comments.
* Add comment.
* Fix missing filter.
* Address second round of comments from Jacqui.
* Make jumps, logic, and syscalls read from/write to memory columns
* Change CTL convention (outputs precede inputs)
* Change convention so outputs follow inputs in memory channel order
I was thinking we could have two sets of shared columns:
- First, a set of "core" columns which would contain instruction decoding registers during an execution cycle, or some counter data during a kernel bootloading cycle.
- Second, a set of "general" columns which would be more general-purpose. For now it could contain "looking" columns for most CTLs (Keccak, arithmetic and logic; NOT memory since memory can be used simultaneously with the others). It could potentially be reused for other things too, such as the registers used for `EQ` and `IS_ZERO` (but I know it's nontrivial to share those since we would need to use lower-degree constraints, so I wouldn't bother for now).
This PR implements just the latter. If it looks good I'll proceed with the former afterward.
