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31 Commits

Author SHA1 Message Date
Jacqueline Nabaglo
f3946f75bf
Gas constraints (#880) 
* Gas constraints

* Bugfix

* make test pass post rebase
 2023-02-14 22:30:19 -08:00
Hamish Ivey-Law
40866e775a
Refactor arithmetic operation traits (#876) 
* Use U256s in `generate(...)` interfaces; fix reduction bug modular.

* Refactor `Operation` trait.

* Rename file.

* Rename `add_cc` things to `addcy`.

* Clippy.

* Simplify generation of less-than and greater-than.

* Add some comparison tests.

* Use `PrimeField64` instead of `RichField` where possible.

* Connect `SUBMOD` operation to witness generator.

* Add clippy exception.

* Add missing verification of range counter column.

* Fix generation of RANGE_COUNTER column.

* Address William's PR comments.
 2023-02-10 23:07:57 +11:00
Jacqueline Nabaglo
b6bc018cba
Simplify JUMP/JUMPI constraints and finish witness generation (#846) 
* Simplify `JUMP`/`JUMPI` constraints and finish witness generation

* Constrain stack
 2022-12-11 11:08:33 -08:00
Daniel Lubarov
b8b2fefe52 Use Keccak sponge table for bootloading 
And get rid of the deprecated Keccak memory table.
 2022-12-03 11:21:31 -08:00
Daniel Lubarov
526dc9bb77 Flush out operation list 2022-11-30 21:00:48 -08:00
Daniel Lubarov
afb3e4b1e1 Misc work on witness generation 2022-11-30 14:58:40 -08:00
Daniel Lubarov
206f527338 Merge branch 'main' into jacqui/witness-generation 2022-11-30 10:09:57 -08:00
Jacqueline Nabaglo
87a9c002c9 Compiler errors + refactor 2022-11-28 13:19:40 -08:00
Hamish Ivey-Law
1c87fbb712
EVM shift left/right operations (#801) 
* First parts of shift implementation.

* Disable range check errors.

* Tidy up ASM.

* Update comments; fix some .sum() expressions.

* First full draft of shift left/right.

* Missed a +1.

* Clippy.

* Address Jacqui's comments.

* Add comment.

* Fix missing filter.

* Address second round of comments from Jacqui.
 2022-11-09 10:47:15 +11:00
Jacqueline Nabaglo
626c2583de
Combine all syscalls into one flag (#802) 
* Combine all syscalls into one flag

* Minor: typo

* Daniel PR comments
 2022-11-07 12:29:28 -08:00
Jacqueline Nabaglo
ec3391f9c4
Add Fp254 ops to the CPU table (#779) 
* Add Fp254 ops to the CPU table

* Add forgotten file
 2022-10-13 14:02:19 -07:00
Daniel Lubarov
9e483528d3 MPT hashing logic, part 3 2022-10-02 09:11:39 -07:00
Jacqueline Nabaglo
e978425b26
Connect stack to memory (#735) 
* Connect stack to memory

* Daniel PR comment
 2022-09-28 15:18:56 -07:00
Jacqueline Nabaglo
084700a7f4
Memory channel for program counter (#717) 2022-09-22 18:09:23 -07:00
Jacqueline Nabaglo
cae5f4870c
Stack pointer + underflow/overflow checks (#710) 
* Stack pointer + underflow/overflow checks

* Daniel comments

* Extra docs
 2022-09-10 13:20:30 -07:00
Daniel Lubarov
2c77247d43 Keccak sponge STARK 
It contains a row for each absorb step of the sponge.
 2022-09-01 09:41:19 -07:00
Jacqueline Nabaglo
4c52d37546
Save columns by verifying invalid opcodes in software (#701) 
* Save columns by verifying invalid opcodes in software

* Autogenerate invalid opcode bitfield (Daniel comment)

* Remove unnecessary panic label
 2022-08-30 13:06:03 -07:00
Jacqueline Nabaglo
013bf6471d
Transpose memory columns (make it an array of channel structs) (#700) 2022-08-26 22:05:16 -07:00
Jacqueline Nabaglo
f48de368a9
Make jumps, logic, and syscalls read from/write to memory columns (#699) 
* Make jumps, logic, and syscalls read from/write to memory columns

* Change CTL convention (outputs precede inputs)

* Change convention so outputs follow inputs in memory channel order
 2022-08-26 14:39:39 -07:00
Daniel Lubarov
9671c1e535
Merge pull request #669 from mir-protocol/keccak_memory 
Keccak memory stark
 2022-08-25 15:55:48 -07:00
Jacqueline Nabaglo
f1a5b7b2d1
Delete opcode column (#672) 2022-08-25 11:56:25 -05:00
Daniel Lubarov
522cac5e15 Keccak memory stark 2022-08-24 09:29:17 -07:00
Jacqueline Nabaglo
5922c58730
Change logic limb size to 32 bits (#674) 
* Change logic limb size to 32 bits

* Remove unnecessary columns (thx Daniel!)
 2022-08-17 21:19:27 -07:00
Jacqueline Nabaglo
b98dd47820
Permission levels, jumps, traps (#653) 
* Permission levels, jumps, traps

* Tests passing

* PR comments + documentation

* Docs + minor bugfixes

* Tests

* Use already-defined `stop` and `exception` (but renamed to `sys_stop`, `fault_exception`)

* Daniel comments
 2022-08-16 09:46:10 -07:00
Daniel Lubarov
cc61c7211c Core transaction processing logic 
With lots of TODOs to fill in afterward; this is just a start.
 2022-08-12 17:20:18 -07:00
Jacqueline Nabaglo
24bb632358
Implement PANIC instruction (#644) 
* Implement PANIC instruction

* Minor: comments
 2022-07-29 12:04:42 -07:00
Jacqueline Nabaglo
16c2bee4b9
Increment program counter on native instructions (#641) 2022-07-28 17:30:20 -07:00
Daniel Lubarov
b2f09881c0 Merge branch 'main' into cpu_shared_cols 2022-07-28 13:41:46 -07:00
Daniel Lubarov
6ee2e4fcd8 move 2022-07-18 12:21:29 -07:00
Daniel Lubarov
49a785f2bd rename 2022-07-18 12:21:00 -07:00
Daniel Lubarov
3d83d63f0b Shared CPU columns 
I was thinking we could have two sets of shared columns:
- First, a set of "core" columns which would contain instruction decoding registers during an execution cycle, or some counter data during a kernel bootloading cycle.
- Second, a set of "general" columns which would be more general-purpose. For now it could contain "looking" columns for most CTLs (Keccak, arithmetic and logic; NOT memory since memory can be used simultaneously with the others). It could potentially be reused for other things too, such as the registers used for `EQ` and `IS_ZERO` (but I know it's nontrivial to share those since we would need to use lower-degree constraints, so I wouldn't bother for now).

This PR implements just the latter. If it looks good I'll proceed with the former afterward.
 2022-07-18 12:15:41 -07:00