* Combine FP254 flags
* Combine basic binary ops together and do CTL with opcode value
* Combine ternary ops together
* Combine MUL DIV and MOD
* Combine shift operations
* Combine byte with other binary ops
* Fix tests
* Clean leftover comment
* Update from latest main
* Put the 'is_simulated' flag inside the Operation enum
* Cleaner way to handle "simulated" operations SHL and SHR.
* Fix comments.
* Minor: suggestion for re-expressing `combined_ops`.
* Update comment
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Co-authored-by: Hamish Ivey-Law <hamish@ivey-law.name>
* First draft of linking arithmetic Stark into the CTL mechanism.
* Handle {ADD,SUB,MUL}FP254 operations explicitly in `modular.rs`.
* Adjust argument order; add tests.
* Add CTLs for ADD, MUL, SUB, LT and GT.
* Add CTLs for {ADD,MUL,SUB}MOD, DIV and MOD.
* Add CTLs for {ADD,MUL,SUB}FP254 operations.
* Refactor the CPU/arithmetic CTL mapping; add some documentation.
* Minor comment fixes.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Combine addcy CTLs at the expense of repeated constraint evaluation.
* Merge `*FP254` CTL into main CTL; rename some registers.
* Connect extra argument from CPU in binary ops to facilitate combining with ternary ops.
* Merge modular ops CTL into main CTL.
* Refactor DIV and MOD code into its own module.
* Merge DIV and MOD into arithmetic CTL.
* Clippy.
* Fixes related to merge.
* Simplify register naming.
* Generate u16 BN254 modulus limbs at compile time.
* Clippy.
* Add degree bits ranges for Arithmetic table.
