This commit is contained in:
wborgeaud 2021-08-13 16:39:26 +02:00
parent 611c1767b1
commit d0aae8c2a7
2 changed files with 19 additions and 24 deletions

View File

@ -215,7 +215,6 @@ impl<F: Extendable<D>, const D: usize> CircuitBuilder<F, D> {
precomputed_reduced_evals: PrecomputedReducedEvalsTarget<D>,
common_data: &CommonCircuitData<F, D>,
) -> ExtensionTarget<D> {
println!("combine initial: {}", self.num_gates());
assert!(D > 1, "Not implemented for D=1.");
let config = self.config.clone();
let degree_log = common_data.degree_bits;
@ -252,7 +251,6 @@ impl<F: Extendable<D>, const D: usize> CircuitBuilder<F, D> {
sum = self.div_add_extension(single_numerator, vanish_zeta, sum);
alpha.reset();
println!("done single: {}", self.num_gates());
// Polynomials opened at `x` and `g x`, i.e., the Zs polynomials.
let zs_evals = proof
.unsalted_evals(PlonkPolynomials::ZS_PARTIAL_PRODUCTS, config.zero_knowledge)
@ -276,7 +274,6 @@ impl<F: Extendable<D>, const D: usize> CircuitBuilder<F, D> {
let (mut sum, zs_denominator) =
alpha.shift_and_mul(sum, vanish_zeta, vanish_zeta_right, self);
sum = self.div_add_extension(zs_numerator, zs_denominator, sum);
println!("done doubles: {}", self.num_gates());
sum
}
@ -294,7 +291,6 @@ impl<F: Extendable<D>, const D: usize> CircuitBuilder<F, D> {
round_proof: &FriQueryRoundTarget<D>,
common_data: &CommonCircuitData<F, D>,
) {
println!("query round: {}", self.num_gates());
let config = &common_data.config.fri_config;
let n_log = log2_strict(n);
// TODO: Do we need to range check `x_index` to a target smaller than `p`?
@ -353,7 +349,6 @@ impl<F: Extendable<D>, const D: usize> CircuitBuilder<F, D> {
);
for (i, &arity_bits) in config.reduction_arity_bits.iter().enumerate() {
println!("query round, {}-th arity: {}", i, self.num_gates());
let evals = &round_proof.steps[i].evals;
// Split x_index into the index of the coset x is in, and the index of x within that coset.

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@ -68,25 +68,25 @@ pub(crate) fn prove<F: Extendable<D>, const D: usize>(
partial_witness.full_witness(degree, num_wires)
);
{
let mut count = 0;
let mut count_bad = 0;
for i in 0..degree {
if prover_data.gate_instances[i].gate_ref.0.id()
!= "ArithmeticExtensionGate".to_string()
{
continue;
}
count += 1;
let row = witness.wire_values.iter().map(|c| c[i]).collect::<Vec<_>>();
// println!("{} {:?}", i, &row);
if row[16..].iter().all(|x| x.is_zero()) {
println!("{} {:?}", i, row);
count_bad += 1;
}
}
println!("{} {}", count, count_bad);
}
// {
// let mut count = 0;
// let mut count_bad = 0;
// for i in 0..degree {
// if prover_data.gate_instances[i].gate_ref.0.id()
// != "ArithmeticExtensionGate".to_string()
// {
// continue;
// }
// count += 1;
// let row = witness.wire_values.iter().map(|c| c[i]).collect::<Vec<_>>();
// // println!("{} {:?}", i, &row);
// if row[16..].iter().all(|x| x.is_zero()) {
// println!("{} {:?}", i, row);
// count_bad += 1;
// }
// }
// println!("{} {}", count, count_bad);
// }
let wires_values: Vec<PolynomialValues<F>> = timed!(
timing,