Merge pull request #393 from mir-protocol/remove_bits_fn

Replace `bits()` function with `BITS` const

src/field/fft.rs

@@ -43,7 +43,7 @@ fn fft_dispatch<F: Field>(
     } else {
         Some(fft_root_table(input.len()))
     };
-    let used_root_table = root_table.or_else(|| computed_root_table.as_ref()).unwrap();
+    let used_root_table = root_table.or(computed_root_table.as_ref()).unwrap();
 
     fft_classic(input, zero_factor.unwrap_or(0), used_root_table)
 }

src/field/field_types.rs

@@ -59,6 +59,7 @@ pub trait Field:
     /// Generator of a multiplicative subgroup of order `2^TWO_ADICITY`.
     const POWER_OF_TWO_GENERATOR: Self;
 
+    /// The bit length of the field order.
     const BITS: usize;
 
     fn order() -> BigUint;
@@ -407,11 +408,6 @@ pub trait Field:
 pub trait PrimeField: Field<PrimeField = Self> {
     const ORDER: u64;
 
-    /// The number of bits required to encode any field element.
-    fn bits() -> usize {
-        bits_u64(Self::NEG_ONE.to_canonical_u64())
-    }
-
     fn to_canonical_u64(&self) -> u64;
 
     fn to_noncanonical_u64(&self) -> u64;

src/fri/recursive_verifier.rs

@@ -338,7 +338,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
         // verify that this has a negligible impact on soundness error.
         Self::assert_noncanonical_indices_ok(&common_data.config);
         let x_index = challenger.get_challenge(self);
-        let mut x_index_bits = self.low_bits(x_index, n_log, F::bits());
+        let mut x_index_bits = self.low_bits(x_index, n_log, F::BITS);
 
         let cap_index =
             self.le_sum(x_index_bits[x_index_bits.len() - common_data.config.cap_height..].iter());

src/gadgets/sorting.rs

@@ -128,8 +128,7 @@ impl<F: RichField + Extendable<D>, const D: usize> SimpleGenerator<F>
     fn dependencies(&self) -> Vec<Target> {
         self.input_ops
             .iter()
-            .map(|op| vec![op.is_write.target, op.address, op.timestamp, op.value])
-            .flatten()
+            .flat_map(|op| vec![op.is_write.target, op.address, op.timestamp, op.value])
             .collect()
     }
 

src/gates/base_sum.rs

@@ -24,7 +24,7 @@ impl<const B: usize> BaseSumGate<B> {
     }
 
     pub fn new_from_config<F: PrimeField>(config: &CircuitConfig) -> Self {
-        let num_limbs = F::bits().min(config.num_routed_wires - Self::START_LIMBS);
+        let num_limbs = F::BITS.min(config.num_routed_wires - Self::START_LIMBS);
         Self::new(num_limbs)
     }