From 4305a95cdbd51ff74b4b04d46b56e3e8a93034bc Mon Sep 17 00:00:00 2001
From: wborgeaud <williamborgeaud@gmail.com>
Date: Tue, 21 Sep 2021 12:52:28 +0200
Subject: [PATCH 1/2] Small fixes to the `le_sum` and `reduce` gadgets

---
 src/gadgets/split_base.rs | 3 +++
 src/util/reducing.rs      | 8 +-------
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/src/gadgets/split_base.rs b/src/gadgets/split_base.rs
index 0d5c9906..582f9286 100644
--- a/src/gadgets/split_base.rs
+++ b/src/gadgets/split_base.rs
@@ -32,6 +32,9 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
         bits: impl ExactSizeIterator<Item = impl Borrow<BoolTarget>> + Clone,
     ) -> Target {
         let num_bits = bits.len();
+        if num_bits == 0 {
+            return self.zero();
+        }
         debug_assert!(
             BaseSumGate::<2>::START_LIMBS + num_bits <= self.config.num_routed_wires,
             "Not enough routed wires."
diff --git a/src/util/reducing.rs b/src/util/reducing.rs
index 3fc0845c..a729662a 100644
--- a/src/util/reducing.rs
+++ b/src/util/reducing.rs
@@ -137,12 +137,6 @@ impl<const D: usize> ReducingFactorTarget<D> {
         acc
     }
 
-    /// Reduces a length `n` vector of `ExtensionTarget`s using `n/2` `ArithmeticExtensionGate`s.
-    /// It does this by batching two steps of Horner's method in each gate.
-    /// Here's an example with `n=4, alpha=2, D=1`:
-    /// 1st gate: 2  0 4  4 3  4 11 <- 2*0+4=4, 2*4+3=11
-    /// 2nd gate: 2 11 2 24 1 24 49 <- 2*11+2=24, 2*24+1=49
-    /// which verifies that `2.reduce([1,2,3,4]) = 49`.
     pub fn reduce<F>(
         &mut self,
         terms: &[ExtensionTarget<D>], // Could probably work with a `DoubleEndedIterator` too.
@@ -155,7 +149,7 @@ impl<const D: usize> ReducingFactorTarget<D> {
         self.count += l as u64;
 
         let mut terms_vec = terms.to_vec();
-        let mut acc = terms_vec.pop().unwrap();
+        let mut acc = builder.zero_extension();
         terms_vec.reverse();
 
         for x in terms_vec {

From 5f3a5e6bad3729c05b28b7798e9995e55f02b12a Mon Sep 17 00:00:00 2001
From: wborgeaud <williamborgeaud@gmail.com>
Date: Tue, 21 Sep 2021 18:27:49 +0200
Subject: [PATCH 2/2] Add `num_bits==1,2` cases in `le_sum`

---
 src/gadgets/split_base.rs | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/gadgets/split_base.rs b/src/gadgets/split_base.rs
index 582f9286..1023e277 100644
--- a/src/gadgets/split_base.rs
+++ b/src/gadgets/split_base.rs
@@ -34,6 +34,15 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
         let num_bits = bits.len();
         if num_bits == 0 {
             return self.zero();
+        } else if num_bits == 1 {
+            let mut bits = bits;
+            return bits.next().unwrap().borrow().target;
+        } else if num_bits == 2 {
+            let two = self.two();
+            let mut bits = bits;
+            let b0 = bits.next().unwrap().borrow().target;
+            let b1 = bits.next().unwrap().borrow().target;
+            return self.mul_add(two, b1, b0);
         }
         debug_assert!(
             BaseSumGate::<2>::START_LIMBS + num_bits <= self.config.num_routed_wires,