From 7cbce7bf6db967bf98e36045f1ebab005334a90a Mon Sep 17 00:00:00 2001 From: Jacqueline Nabaglo Date: Wed, 15 Jun 2022 11:27:40 -0700 Subject: [PATCH] Remove redundant constraints (#568) --- evm/src/cpu/decode.rs | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/evm/src/cpu/decode.rs b/evm/src/cpu/decode.rs index d9f4c60a..5cd132a0 100644 --- a/evm/src/cpu/decode.rs +++ b/evm/src/cpu/decode.rs @@ -163,10 +163,6 @@ pub fn eval_packed_generic( ) { let cycle_filter = lv[columns::IS_CPU_CYCLE]; - // If cycle_filter = 0, then we require is_eq = 0 and is_iszero = 0. - yield_constr.constraint((cycle_filter - P::ONES) * lv[columns::IS_EQ]); - yield_constr.constraint((cycle_filter - P::ONES) * lv[columns::IS_ISZERO]); - // Ensure that the opcode bits are valid: each has to be either 0 or 1, and they must match // the opcode. Note that this also validates that this implicitly range-checks the opcode. let bits = columns::OPCODE_BITS.map(|i| lv[i]); @@ -214,12 +210,6 @@ pub fn eval_ext_circuit, const D: usize>( ) { let cycle_filter = lv[columns::IS_CPU_CYCLE]; - // If cycle_filter = 0, then we require is_eq = 0 and is_iszero = 0. - for flag in [lv[columns::IS_EQ], lv[columns::IS_ISZERO]] { - let constr = builder.mul_sub_extension(cycle_filter, flag, flag); - yield_constr.constraint(builder, constr); - } - // Ensure that the opcode bits are valid: each has to be either 0 or 1, and they must match // the opcode. Note that this also validates that this implicitly range-checks the opcode. let bits = columns::OPCODE_BITS.map(|i| lv[i]);