logos-storage/plonky2
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This commit is contained in:
wborgeaud 2021-10-18 21:38:57 +02:00
parent c7674b24ba
commit 5f4a244240
3 changed files with 11 additions and 15 deletions
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15
src/fri/recursive_verifier.rs
View File

@ -59,11 +59,12 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
/// Make sure we have enough wires and routed wires to do the FRI checks efficiently. This check
/// isn't required -- without it we'd get errors elsewhere in the stack -- but just gives more
/// helpful errors.
fn check_config(&self, arity: usize) {
// TODO: It would be nice to remove the hardcoded 8 here and replace it with the maximum arity bits
// used in FRI.
let random_access = RandomAccessGate::<F, D>::new_from_config(&self.config, 8);
let interpolation_gate = InterpolationGate::<F, D>::new(arity);
fn check_config(&self, max_fri_arity: usize) {
let random_access = RandomAccessGate::<F, D>::new_from_config(
&self.config,
max_fri_arity.max(1 << self.config.cap_height),
);
let interpolation_gate = InterpolationGate::<F, D>::new(max_fri_arity);
let min_wires = random_access
.num_wires()
@ -75,14 +76,14 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
assert!(
self.config.num_wires >= min_wires,
"To efficiently perform FRI checks with an arity of {}, at least {} wires are needed. Consider reducing arity.",
arity,
max_fri_arity,
min_wires
);
assert!(
self.config.num_routed_wires >= min_routed_wires,
"To efficiently perform FRI checks with an arity of {}, at least {} routed wires are needed. Consider reducing arity.",
arity,
max_fri_arity,
min_routed_wires
);
}

4
src/gates/random_access.rs
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@ -37,8 +37,8 @@ impl<F: RichField + Extendable<D>, const D: usize> RandomAccessGate<F, D> {
pub fn max_num_copies(num_routed_wires: usize, num_wires: usize, vec_size: usize) -> usize {
// Need `(2 + vec_size) * num_copies` routed wires
(num_routed_wires / (2 + vec_size)).min(
// Need `(2 + 4*vec_size) * num_copies` wires
num_wires / (2 + 4 * vec_size),
// Need `(2 + 3*vec_size) * num_copies` wires
num_wires / (2 + 3 * vec_size),
)
}

7
src/plonk/circuit_builder.rs
View File

@ -540,12 +540,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
/// `RandomAccessGenerator`s are run.
fn fill_random_access_gates(&mut self) {
let zero = self.zero();
let remaining_random_access_gates = self
.free_random_access
.clone()
.into_iter()
.collect::<Vec<_>>();
for (vec_size, (_, i)) in remaining_random_access_gates {
for (vec_size, (_, i)) in self.free_random_access.clone() {
let max_copies = RandomAccessGate::<F, D>::max_num_copies(
self.config.num_routed_wires,
self.config.num_wires,