From 5f3a5e6bad3729c05b28b7798e9995e55f02b12a Mon Sep 17 00:00:00 2001
From: wborgeaud <williamborgeaud@gmail.com>
Date: Tue, 21 Sep 2021 18:27:49 +0200
Subject: [PATCH] Add `num_bits==1,2` cases in `le_sum`

---
 src/gadgets/split_base.rs | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/gadgets/split_base.rs b/src/gadgets/split_base.rs
index 582f9286..1023e277 100644
--- a/src/gadgets/split_base.rs
+++ b/src/gadgets/split_base.rs
@@ -34,6 +34,15 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
         let num_bits = bits.len();
         if num_bits == 0 {
             return self.zero();
+        } else if num_bits == 1 {
+            let mut bits = bits;
+            return bits.next().unwrap().borrow().target;
+        } else if num_bits == 2 {
+            let two = self.two();
+            let mut bits = bits;
+            let b0 = bits.next().unwrap().borrow().target;
+            let b1 = bits.next().unwrap().borrow().target;
+            return self.mul_add(two, b1, b0);
         }
         debug_assert!(
             BaseSumGate::<2>::START_LIMBS + num_bits <= self.config.num_routed_wires,