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Fix logic CTL
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@ -83,7 +83,9 @@ fn ctl_data_ternops<F: Field>(ops: &[usize], is_shift: bool) -> Vec<Column<F>> {
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}
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}
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pub fn ctl_data_logic<F: Field>() -> Vec<Column<F>> {
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pub fn ctl_data_logic<F: Field>() -> Vec<Column<F>> {
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ctl_data_binops(&[COL_MAP.op.and_or, COL_MAP.op.xor])
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let mut res = vec![Column::le_bits(COL_MAP.opcode_bits)];
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res.extend(ctl_data_binops(&[]));
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res
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}
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}
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pub fn ctl_filter_logic<F: Field>() -> Column<F> {
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pub fn ctl_filter_logic<F: Field>() -> Column<F> {
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@ -103,8 +103,7 @@ pub(crate) fn ctl_looking_logic<F: Field>(i: usize) -> Vec<Column<F>> {
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let cols = KECCAK_SPONGE_COL_MAP;
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let cols = KECCAK_SPONGE_COL_MAP;
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let mut res = vec![
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let mut res = vec![
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Column::zero(), // is_and_or
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Column::constant(F::from_canonical_u8(0x18)), // is_xor
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Column::one(), // is_xor
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];
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];
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// Input 0 contains some of the sponge's original rate chunks. If this is the last CTL, we won't
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// Input 0 contains some of the sponge's original rate chunks. If this is the last CTL, we won't
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@ -52,10 +52,11 @@ pub(crate) mod columns {
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}
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}
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pub fn ctl_data<F: Field>() -> Vec<Column<F>> {
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pub fn ctl_data<F: Field>() -> Vec<Column<F>> {
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let mut res = vec![
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let mut res = vec![Column::linear_combination([
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Column::sum([columns::IS_AND, columns::IS_OR]),
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(columns::IS_AND, F::from_canonical_u8(0x16)),
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Column::single(columns::IS_XOR),
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(columns::IS_OR, F::from_canonical_u8(0x17)),
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];
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(columns::IS_XOR, F::from_canonical_u8(0x18)),
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])];
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res.extend(columns::limb_bit_cols_for_input(columns::INPUT0).map(Column::le_bits));
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res.extend(columns::limb_bit_cols_for_input(columns::INPUT0).map(Column::le_bits));
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res.extend(columns::limb_bit_cols_for_input(columns::INPUT1).map(Column::le_bits));
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res.extend(columns::limb_bit_cols_for_input(columns::INPUT1).map(Column::le_bits));
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res.extend(columns::RESULT.map(Column::single));
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res.extend(columns::RESULT.map(Column::single));
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