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Merge pull request #290 from mir-protocol/trivial_random_access

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Add check for trivial random access
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wborgeaud 2021-10-07 08:37:42 +02:00 committed by GitHub
commit 145ee8cb18
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1 changed files with 8 additions and 0 deletions
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8
src/gadgets/random_access.rs
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@ -14,6 +14,10 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
claimed_element: ExtensionTarget<D>, claimed_element: ExtensionTarget<D>,
v: Vec<ExtensionTarget<D>>, v: Vec<ExtensionTarget<D>>,
) { ) {
debug_assert!(!v.is_empty());
if v.len() == 1 {
return self.connect_extension(claimed_element, v[0]);
}
let gate = RandomAccessGate::new(v.len()); let gate = RandomAccessGate::new(v.len());
let gate_index = self.add_gate(gate.clone(), vec![]); let gate_index = self.add_gate(gate.clone(), vec![]);
@ -42,6 +46,10 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
mut v: Vec<ExtensionTarget<D>>, mut v: Vec<ExtensionTarget<D>>,
min_length: usize, min_length: usize,
) { ) {
debug_assert!(!v.is_empty());
if v.len() == 1 {
return self.connect_extension(claimed_element, v[0]);
}
let zero = self.zero_extension(); let zero = self.zero_extension();
if v.len() < min_length { if v.len() < min_length {
v.resize(8, zero); v.resize(8, zero);