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Remove params in GateInstance

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This commit is contained in:
wborgeaud 2022-02-16 09:02:21 +01:00
parent 661a6b44ef
commit 08e255a2bb
15 changed files with 25 additions and 32 deletions
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2
insertion/src/insert_gadget.rs
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@ -27,7 +27,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilderInsert<F, D>
v: Vec<ExtensionTarget<D>>,
) -> Vec<ExtensionTarget<D>> {
let gate = InsertionGate::new(v.len());
let gate_index = self.add_gate(gate.clone(), vec![], vec![]);
let gate_index = self.add_gate(gate.clone(), vec![]);
v.iter().enumerate().for_each(|(i, &val)| {
self.connect_extension(

2
plonky2/src/gadgets/arithmetic.rs
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@ -241,7 +241,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
while exp_bits_vec.len() < num_power_bits {
exp_bits_vec.push(_false);
}
let gate_index = self.add_gate(gate.clone(), vec![], vec![]);
let gate_index = self.add_gate(gate.clone(), vec![]);
self.connect(base, Target::wire(gate_index, gate.wire_base()));
exp_bits_vec.iter().enumerate().for_each(|(i, bit)| {

2
plonky2/src/gadgets/interpolation.rs
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@ -88,7 +88,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
evaluation_point: ExtensionTarget<D>,
) -> ExtensionTarget<D> {
let gate = G::new(subgroup_bits);
let gate_index = self.add_gate(gate, vec![], vec![]);
let gate_index = self.add_gate(gate, vec![]);
self.connect(coset_shift, Target::wire(gate_index, gate.wire_shift()));
for (i, &v) in values.iter().enumerate() {
self.connect_extension(

4
plonky2/src/gadgets/multiple_comparison.rs
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@ -25,7 +25,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
let mut result = one;
for i in 0..n {
let a_le_b_gate = ComparisonGate::new(num_bits, num_chunks);
let a_le_b_gate_index = self.add_gate(a_le_b_gate.clone(), vec![], vec![]);
let a_le_b_gate_index = self.add_gate(a_le_b_gate.clone(), vec![]);
self.connect(
Target::wire(a_le_b_gate_index, a_le_b_gate.wire_first_input()),
a[i],
@ -37,7 +37,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
let a_le_b_result = Target::wire(a_le_b_gate_index, a_le_b_gate.wire_result_bool());
let b_le_a_gate = ComparisonGate::new(num_bits, num_chunks);
let b_le_a_gate_index = self.add_gate(b_le_a_gate.clone(), vec![], vec![]);
let b_le_a_gate_index = self.add_gate(b_le_a_gate.clone(), vec![]);
self.connect(
Target::wire(b_le_a_gate_index, b_le_a_gate.wire_first_input()),
b[i],

2
plonky2/src/gadgets/range_check.rs
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@ -47,7 +47,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
pub fn range_check_u32(&mut self, vals: Vec<U32Target>) {
let num_input_limbs = vals.len();
let gate = U32RangeCheckGate::<F, D>::new(num_input_limbs);
let gate_index = self.add_gate(gate, vec![], vec![]);
let gate_index = self.add_gate(gate, vec![]);
for i in 0..num_input_limbs {
self.connect(

4
plonky2/src/gadgets/split_base.rs
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@ -16,7 +16,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
/// base-B limb of the element, with little-endian ordering.
pub fn split_le_base<const B: usize>(&mut self, x: Target, num_limbs: usize) -> Vec<Target> {
let gate_type = BaseSumGate::<B>::new(num_limbs);
let gate = self.add_gate(gate_type, vec![], vec![]);
let gate = self.add_gate(gate_type, vec![]);
let sum = Target::wire(gate, BaseSumGate::<B>::WIRE_SUM);
self.connect(x, sum);
@ -54,7 +54,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
"Not enough routed wires."
);
let gate_type = BaseSumGate::<2>::new_from_config::<F>(&self.config);
let gate_index = self.add_gate(gate_type, vec![], vec![]);
let gate_index = self.add_gate(gate_type, vec![]);
for (limb, wire) in bits
.iter()
.zip(BaseSumGate::<2>::START_LIMBS..BaseSumGate::<2>::START_LIMBS + num_bits)

2
plonky2/src/gadgets/split_join.rs
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@ -20,7 +20,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
let gate_type = BaseSumGate::<2>::new_from_config::<F>(&self.config);
let k = ceil_div_usize(num_bits, gate_type.num_limbs);
let gates = (0..k)
.map(|_| self.add_gate(gate_type, vec![], vec![]))
.map(|_| self.add_gate(gate_type, vec![]))
.collect::<Vec<_>>();
let mut bits = Vec::with_capacity(num_bits);

1
plonky2/src/gates/gate.rs
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@ -189,7 +189,6 @@ pub struct CurrentSlot<F: RichField + Extendable<D>, const D: usize> {
pub struct GateInstance<F: RichField + Extendable<D>, const D: usize> {
pub gate_ref: GateRef<F, D>,
pub constants: Vec<F>,
pub params: Vec<F>,
}
/// Map each gate to a boolean prefix used to construct the gate's selector polynomial.

2
plonky2/src/gates/poseidon.rs
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@ -559,7 +559,7 @@ mod tests {
let mut builder = CircuitBuilder::new(config);
type Gate = PoseidonGate<F, D>;
let gate = Gate::new();
let gate_index = builder.add_gate(gate, vec![], vec![]);
let gate_index = builder.add_gate(gate, vec![]);
let circuit = builder.build_prover::<C>();
let permutation_inputs = (0..SPONGE_WIDTH)

4
plonky2/src/hash/poseidon.rs
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@ -269,7 +269,7 @@ pub trait Poseidon: PrimeField64 {
// If we have enough routed wires, we will use PoseidonMdsGate.
let mds_gate = PoseidonMdsGate::<Self, D>::new();
if builder.config.num_routed_wires >= mds_gate.num_wires() {
let index = builder.add_gate(mds_gate, vec![], vec![]);
let index = builder.add_gate(mds_gate, vec![]);
for i in 0..WIDTH {
let input_wire = PoseidonMdsGate::<Self, D>::wires_input(i);
builder.connect_extension(state[i], ExtensionTarget::from_range(index, input_wire));
@ -652,7 +652,7 @@ impl<F: RichField> AlgebraicHasher<F> for PoseidonHash {
F: RichField + Extendable<D>,
{
let gate_type = PoseidonGate::<F, D>::new();
let gate = builder.add_gate(gate_type, vec![], vec![]);
let gate = builder.add_gate(gate_type, vec![]);
let swap_wire = PoseidonGate::<F, D>::WIRE_SWAP;
let swap_wire = Target::wire(gate, swap_wire);

20
plonky2/src/plonk/circuit_builder.rs
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@ -206,12 +206,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
}
/// Adds a gate to the circuit, and returns its index.
pub fn add_gate<G: Gate<F, D>>(
&mut self,
gate_type: G,
constants: Vec<F>,
params: Vec<F>,
) -> usize {
pub fn add_gate<G: Gate<F, D>>(&mut self, gate_type: G, constants: Vec<F>) -> usize {
self.check_gate_compatibility(&gate_type);
assert_eq!(
gate_type.num_constants(),
@ -232,7 +227,6 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
self.gate_instances.push(GateInstance {
gate_ref,
constants,
params,
});
index
@ -417,7 +411,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
let res = if let Some(&s) = slot {
s
} else {
self.add_gate(gate, constants.to_vec(), params.to_vec());
self.add_gate(gate, constants.to_vec());
(num_gates, 0)
};
if res.1 == num_ops - 1 {
@ -523,7 +517,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
}
while !self.gate_instances.len().is_power_of_two() {
self.add_gate(NoopGate, vec![], vec![]);
self.add_gate(NoopGate, vec![]);
}
}
@ -540,7 +534,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
// For each "regular" blinding factor, we simply add a no-op gate, and insert a random value
// for each wire.
for _ in 0..regular_poly_openings {
let gate = self.add_gate(NoopGate, vec![], vec![]);
let gate = self.add_gate(NoopGate, vec![]);
for w in 0..num_wires {
self.add_simple_generator(RandomValueGenerator {
target: Target::Wire(Wire { gate, input: w }),
@ -552,8 +546,8 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
// enforce a copy constraint between them.
// See https://mirprotocol.org/blog/Adding-zero-knowledge-to-Plonk-Halo
for _ in 0..z_openings {
let gate_1 = self.add_gate(NoopGate, vec![], vec![]);
let gate_2 = self.add_gate(NoopGate, vec![], vec![]);
let gate_1 = self.add_gate(NoopGate, vec![]);
let gate_2 = self.add_gate(NoopGate, vec![]);
for w in 0..num_routed_wires {
self.add_simple_generator(RandomValueGenerator {
@ -670,7 +664,7 @@ impl<F: RichField + Extendable<D>, const D: usize> CircuitBuilder<F, D> {
let num_public_inputs = self.public_inputs.len();
let public_inputs_hash =
self.hash_n_to_hash_no_pad::<C::InnerHasher>(self.public_inputs.clone());
let pi_gate = self.add_gate(PublicInputGate, vec![], vec![]);
let pi_gate = self.add_gate(PublicInputGate, vec![]);
for (&hash_part, wire) in public_inputs_hash
.elements
.iter()

2
plonky2/src/plonk/proof.rs
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@ -411,7 +411,7 @@ mod tests {
let comp_zt = builder.mul(xt, yt);
builder.connect(zt, comp_zt);
for _ in 0..100 {
builder.add_gate(NoopGate, vec![], vec![]);
builder.add_gate(NoopGate, vec![]);
}
let data = builder.build::<C>();
let proof = data.prove(pw)?;

4
plonky2/src/plonk/recursive_verifier.rs
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@ -330,7 +330,7 @@ mod tests {
{
let mut builder = CircuitBuilder::<F, D>::new(config.clone());
for _ in 0..num_dummy_gates {
builder.add_gate(NoopGate, vec![], vec![]);
builder.add_gate(NoopGate, vec![]);
}
let data = builder.build::<C>();
@ -388,7 +388,7 @@ mod tests {
// builder will pad to the next power of two, 2^min_degree_bits.
let min_gates = (1 << (min_degree_bits - 1)) + 1;
for _ in builder.num_gates()..min_gates {
builder.add_gate(NoopGate, vec![], vec![]);
builder.add_gate(NoopGate, vec![]);
}
}

4
plonky2/src/util/reducing.rs
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@ -132,7 +132,7 @@ impl<const D: usize> ReducingFactorTarget<D> {
reversed_terms.reverse();
for chunk in reversed_terms.chunks_exact(max_coeffs_len) {
let gate = ReducingGate::new(max_coeffs_len);
let gate_index = builder.add_gate(gate.clone(), vec![], vec![]);
let gate_index = builder.add_gate(gate.clone(), vec![]);
builder.connect_extension(
self.base,
@ -182,7 +182,7 @@ impl<const D: usize> ReducingFactorTarget<D> {
reversed_terms.reverse();
for chunk in reversed_terms.chunks_exact(max_coeffs_len) {
let gate = ReducingExtensionGate::new(max_coeffs_len);
let gate_index = builder.add_gate(gate.clone(), vec![], vec![]);
let gate_index = builder.add_gate(gate.clone(), vec![]);
builder.connect_extension(
self.base,

2
waksman/src/sorting.rs
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@ -54,7 +54,7 @@ pub fn assert_le<F: RichField + Extendable<D>, const D: usize>(
num_chunks: usize,
) {
let gate = AssertLessThanGate::new(bits, num_chunks);
let gate_index = builder.add_gate(gate.clone(), vec![], vec![]);
let gate_index = builder.add_gate(gate.clone(), vec![]);
builder.connect(Target::wire(gate_index, gate.wire_first_input()), lhs);
builder.connect(Target::wire(gate_index, gate.wire_second_input()), rhs);