From 4f61d792bc9c95784247c1cb509f1c8baf9ee505 Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:42:11 +0100 Subject: [PATCH 01/10] add setup_sequencer_config for tests --- sequencer_core/src/lib.rs | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index c6be871..1a9690d 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -254,3 +254,32 @@ impl SequencerCore { Ok(self.chain_height - 1) } } + +#[cfg(test)] +mod tests { + use super::*; + use std::{fmt::format, path::PathBuf}; + + use rand::Rng; + use storage::transaction::{Transaction, TxKind}; + use transaction_mempool::TransactionMempool; + + fn setup_sequencer_config() -> SequencerConfig { + let mut rng = rand::thread_rng(); + let random_u8: u8 = rng.gen(); + + let path_str = format!("/tmp/sequencer_{:?}", random_u8); + + SequencerConfig { + home: PathBuf::from(path_str), + override_rust_log: Some("info".to_string()), + genesis_id: 1, + is_genesis_random: false, + max_num_tx_in_block: 10, + block_create_timeout_millis: 1000, + port: 8080, + } + } + + +} \ No newline at end of file From aa74dae70fa7df38809dad8a6be4283d1598793f Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:42:27 +0100 Subject: [PATCH 02/10] add create_dummy_transaction for tests --- sequencer_core/src/lib.rs | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 1a9690d..032304d 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -281,5 +281,26 @@ mod tests { } } + fn create_dummy_transaction( + hash: TreeHashType, + nullifier_created_hashes: Vec<[u8; 32]>, + utxo_commitments_spent_hashes: Vec<[u8; 32]>, + utxo_commitments_created_hashes: Vec<[u8; 32]>, + ) -> Transaction { + Transaction { + hash, + tx_kind: TxKind::Private, + execution_input: vec![], + execution_output: vec![], + utxo_commitments_spent_hashes, + utxo_commitments_created_hashes, + nullifier_created_hashes, + execution_proof_private: "dummy_proof".to_string(), + encoded_data: vec![], + ephemeral_pub_key: vec![10, 11, 12], + } + } + + } \ No newline at end of file From 91de70b7dc3405387357dc0c8c7c9fe4f1e30a2b Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:42:43 +0100 Subject: [PATCH 03/10] add common_setup for tests --- sequencer_core/src/lib.rs | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 032304d..8197870 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -301,6 +301,17 @@ mod tests { } } + fn common_setup(mut sequencer: &mut SequencerCore) { + let tx = create_dummy_transaction( + [12; 32], + vec![[9; 32]], + vec![[7; 32]], + vec![[8; 32]], + ); + let tx_mempool = TransactionMempool { tx }; + sequencer.mempool.push_item(tx_mempool); + sequencer.produce_new_block_with_mempool_transactions(); + } } \ No newline at end of file From 182adad9d2be49f43d6dcba75f44c9758517847e Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:43:17 +0100 Subject: [PATCH 04/10] add test_start_from_config --- sequencer_core/src/lib.rs | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 8197870..5ebe55b 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -314,4 +314,15 @@ mod tests { sequencer.produce_new_block_with_mempool_transactions(); } + #[test] + fn test_start_from_config() { + let config = setup_sequencer_config(); + let sequencer = SequencerCore::start_from_config(config.clone()); + + assert_eq!(sequencer.chain_height, config.genesis_id); + assert_eq!(sequencer.sequencer_config.max_num_tx_in_block, 10); + assert_eq!(sequencer.sequencer_config.port, 8080); + } + + } \ No newline at end of file From ef1d95ea2d79a4cba4aaba8cae641cab13782408 Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:43:45 +0100 Subject: [PATCH 05/10] add test_get_tree_roots --- sequencer_core/src/lib.rs | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 5ebe55b..226b49d 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -324,5 +324,16 @@ mod tests { assert_eq!(sequencer.sequencer_config.port, 8080); } + #[test] + fn test_get_tree_roots() { + let config = setup_sequencer_config(); + let mut sequencer = SequencerCore::start_from_config(config); + + common_setup(&mut sequencer); + + let roots = sequencer.get_tree_roots(); + assert_eq!(roots.len(), 3); // Should return three roots + } + } \ No newline at end of file From 671a1f29237b76ee51b2a8df3f02258ab962e5a7 Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:44:07 +0100 Subject: [PATCH 06/10] add test_transaction_pre_check_pass --- sequencer_core/src/lib.rs | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 226b49d..75a4abb 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -335,5 +335,24 @@ mod tests { assert_eq!(roots.len(), 3); // Should return three roots } + #[test] + fn test_transaction_pre_check_pass() { + let config = setup_sequencer_config(); + let mut sequencer = SequencerCore::start_from_config(config); + + common_setup(&mut sequencer); + + let tx = create_dummy_transaction( + [1; 32], + vec![[91; 32]], + vec![[71; 32]], + vec![[81; 32]], + ); + let tx_roots = sequencer.get_tree_roots(); + let result = sequencer.transaction_pre_check(&tx, tx_roots); + + assert!(result.is_ok()); + } + } \ No newline at end of file From f2a781545b636d19eb45fb61a5d9db90ab30be16 Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:44:30 +0100 Subject: [PATCH 07/10] add test_transaction_pre_check_fail_mempool_full --- sequencer_core/src/lib.rs | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 75a4abb..8e20480 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -354,5 +354,35 @@ mod tests { assert!(result.is_ok()); } + #[test] + fn test_transaction_pre_check_fail_mempool_full() { + let config = SequencerConfig { + max_num_tx_in_block: 1, + ..setup_sequencer_config() + }; + let mut sequencer = SequencerCore::start_from_config(config); + + common_setup(&mut sequencer); + + let tx = create_dummy_transaction( + [2; 32], + vec![[92; 32]], + vec![[72; 32]], + vec![[82; 32]] + ); + let tx_roots = sequencer.get_tree_roots(); + + // Fill the mempool + let dummy_tx = TransactionMempool { tx: tx.clone() }; + sequencer.mempool.push_item(dummy_tx); + + let result = sequencer.transaction_pre_check(&tx, tx_roots); + + assert!(matches!( + result, + Err(TransactionMalformationErrorKind::MempoolFullForRound { .. }) + )); + } + } \ No newline at end of file From 8d63de52f97c4e9b44e33de3173214ff11466ee9 Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:44:45 +0100 Subject: [PATCH 08/10] add test_push_tx_into_mempool_pre_check --- sequencer_core/src/lib.rs | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 8e20480..d3cb1ca 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -384,5 +384,25 @@ mod tests { )); } + #[test] + fn test_push_tx_into_mempool_pre_check() { + let config = setup_sequencer_config(); + let mut sequencer = SequencerCore::start_from_config(config); + + common_setup(&mut sequencer); + + let tx = create_dummy_transaction( + [3; 32], + vec![[93; 32]], + vec![[73; 32]], + vec![[83; 32]] + ); + let tx_roots = sequencer.get_tree_roots(); + let tx_mempool = TransactionMempool { tx }; + + let result = sequencer.push_tx_into_mempool_pre_check(tx_mempool.clone(), tx_roots); + assert!(result.is_ok()); + assert_eq!(sequencer.mempool.len(), 1); + } } \ No newline at end of file From 01d51c6e4519ffb925756793af334b7daa7ad94d Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:45:01 +0100 Subject: [PATCH 09/10] add test_produce_new_block_with_mempool_transactions --- sequencer_core/src/lib.rs | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index d3cb1ca..993e9f1 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -405,4 +405,22 @@ mod tests { assert_eq!(sequencer.mempool.len(), 1); } + #[test] + fn test_produce_new_block_with_mempool_transactions() { + let config = setup_sequencer_config(); + let mut sequencer = SequencerCore::start_from_config(config); + + let tx = create_dummy_transaction( + [4; 32], + vec![[94; 32]], + vec![[7; 32]], + vec![[8; 32]], + ); + let tx_mempool = TransactionMempool { tx }; + sequencer.mempool.push_item(tx_mempool); + + let block_id = sequencer.produce_new_block_with_mempool_transactions(); + assert!(block_id.is_ok()); + assert_eq!(block_id.unwrap(), 1); + } } \ No newline at end of file From 0e30e64534297b108661be03afd9da1fa6942d5e Mon Sep 17 00:00:00 2001 From: Rostyslav Tyshko Date: Mon, 27 Jan 2025 13:51:27 +0100 Subject: [PATCH 10/10] fmt --- sequencer_core/src/lib.rs | 39 +++++++-------------------------------- 1 file changed, 7 insertions(+), 32 deletions(-) diff --git a/sequencer_core/src/lib.rs b/sequencer_core/src/lib.rs index 993e9f1..c272c49 100644 --- a/sequencer_core/src/lib.rs +++ b/sequencer_core/src/lib.rs @@ -282,7 +282,7 @@ mod tests { } fn create_dummy_transaction( - hash: TreeHashType, + hash: TreeHashType, nullifier_created_hashes: Vec<[u8; 32]>, utxo_commitments_spent_hashes: Vec<[u8; 32]>, utxo_commitments_created_hashes: Vec<[u8; 32]>, @@ -302,12 +302,7 @@ mod tests { } fn common_setup(mut sequencer: &mut SequencerCore) { - let tx = create_dummy_transaction( - [12; 32], - vec![[9; 32]], - vec![[7; 32]], - vec![[8; 32]], - ); + let tx = create_dummy_transaction([12; 32], vec![[9; 32]], vec![[7; 32]], vec![[8; 32]]); let tx_mempool = TransactionMempool { tx }; sequencer.mempool.push_item(tx_mempool); @@ -342,12 +337,7 @@ mod tests { common_setup(&mut sequencer); - let tx = create_dummy_transaction( - [1; 32], - vec![[91; 32]], - vec![[71; 32]], - vec![[81; 32]], - ); + let tx = create_dummy_transaction([1; 32], vec![[91; 32]], vec![[71; 32]], vec![[81; 32]]); let tx_roots = sequencer.get_tree_roots(); let result = sequencer.transaction_pre_check(&tx, tx_roots); @@ -364,12 +354,7 @@ mod tests { common_setup(&mut sequencer); - let tx = create_dummy_transaction( - [2; 32], - vec![[92; 32]], - vec![[72; 32]], - vec![[82; 32]] - ); + let tx = create_dummy_transaction([2; 32], vec![[92; 32]], vec![[72; 32]], vec![[82; 32]]); let tx_roots = sequencer.get_tree_roots(); // Fill the mempool @@ -391,12 +376,7 @@ mod tests { common_setup(&mut sequencer); - let tx = create_dummy_transaction( - [3; 32], - vec![[93; 32]], - vec![[73; 32]], - vec![[83; 32]] - ); + let tx = create_dummy_transaction([3; 32], vec![[93; 32]], vec![[73; 32]], vec![[83; 32]]); let tx_roots = sequencer.get_tree_roots(); let tx_mempool = TransactionMempool { tx }; @@ -410,12 +390,7 @@ mod tests { let config = setup_sequencer_config(); let mut sequencer = SequencerCore::start_from_config(config); - let tx = create_dummy_transaction( - [4; 32], - vec![[94; 32]], - vec![[7; 32]], - vec![[8; 32]], - ); + let tx = create_dummy_transaction([4; 32], vec![[94; 32]], vec![[7; 32]], vec![[8; 32]]); let tx_mempool = TransactionMempool { tx }; sequencer.mempool.push_item(tx_mempool); @@ -423,4 +398,4 @@ mod tests { assert!(block_id.is_ok()); assert_eq!(block_id.unwrap(), 1); } -} \ No newline at end of file +}