50 lines
1.7 KiB
Nim
50 lines
1.7 KiB
Nim
when defined(i386) or defined(amd64):
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# From Linux
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#
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# The RDTSC instruction is not ordered relative to memory
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# access. The Intel SDM and the AMD APM are both vague on this
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# point, but empirically an RDTSC instruction can be
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# speculatively executed before prior loads. An RDTSC
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# immediately after an appropriate barrier appears to be
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# ordered as a normal load, that is, it provides the same
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# ordering guarantees as reading from a global memory location
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# that some other imaginary CPU is updating continuously with a
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# time stamp.
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#
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# From Intel SDM
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# https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ia-32-ia-64-benchmark-code-execution-paper.pdf
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when not defined(vcc):
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when defined(amd64):
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proc getTicks*(): int64 {.inline.} =
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var lo, hi: int64
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# TODO: Provide a compile-time flag for RDTSCP support
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# and use it instead of lfence + RDTSC
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{.emit: """asm volatile(
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"lfence\n"
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"rdtsc\n"
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: "=a"(`lo`), "=d"(`hi`)
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:
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: "memory"
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);""".}
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return (hi shl 32) or lo
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else:
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proc getTicks*(): int64 {.inline.} =
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# TODO: Provide a compile-time flag for RDTSCP support
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# and use it instead of lfence + RDTSC
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{.emit: """asm volatile(
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"lfence\n"
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"rdtsc\n"
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: "=a"(`result`)
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:
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: "memory"
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);""".}
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else:
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proc rdtsc(): int64 {.sideeffect, importc: "__rdtsc", header: "<intrin.h>".}
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proc lfence() {.importc: "__mm_lfence", header: "<intrin.h>".}
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proc getTicks*(): int64 {.inline.} =
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lfence()
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return rdtsc()
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else:
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{.error: "getticks is not supported on this CPU architecture".}
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